diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-07-25 01:23:17 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-16 17:31:48 +0100 |
| commit | dc4cb05763fa029d7495f7aa37194f3ee5abaf05 (patch) | |
| tree | 618b990234696615433d6f3618ccb9d8f3a2ccd9 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | 323a2af8e25ad2ff9b81b58f5fccd4ea7d39e72f (diff) | |
nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots
The current code did not define the number of DIMM slots on the
mainboard, which lead to incorrect configuration values and
occassional training failure.
Add preliminary support for DIMM slot count configuration.
Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12016
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 24 |
1 files changed, 4 insertions, 20 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index c8d72c6702..9d53823632 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -809,11 +809,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) { - /* FIXME - * Mainboards need to be able to specify the maximum number of DIMMs installable per channel - * For now assume a maximum of 2 DIMMs per channel can be installed - */ - uint8_t MaxDimmsInstallable = 2; + uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); uint8_t package_type; uint32_t calibration_code = 0; @@ -989,11 +985,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct) { - /* FIXME - * Mainboards need to be able to specify the maximum number of DIMMs installable per channel - * For now assume a maximum of 2 DIMMs per channel can be installed - */ - uint8_t MaxDimmsInstallable = 2; + uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); uint8_t package_type; uint32_t calibration_code = 0; @@ -1171,11 +1163,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dct) { - /* FIXME - * Mainboards need to be able to specify the maximum number of DIMMs installable per channel - * For now assume a maximum of 2 DIMMs per channel can be installed - */ - uint8_t MaxDimmsInstallable = 2; + uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); uint8_t package_type; uint32_t slow_access = 0; @@ -5878,11 +5866,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Start\n", __func__); - /* FIXME - * Mainboards need to be able to specify the maximum number of DIMMs installable per channel - * For now assume a maximum of 2 DIMMs per channel can be installed - */ - uint8_t MaxDimmsInstallable = 2; + uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); if (is_fam15h()) { /* Obtain number of DIMMs on channel */ |