nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values

During maximum read latency training on Family 15h processors,
the maximum read latency was incorrectly set from the NBP1
value instead of the correct NBP0 value.

Modify maximimum read latency training to explicitly operate
on the NBP0 value, and store the previously calculated NBP1
value for reference by other portions of the training algorithm.

Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14150
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 4615dd2ed0..9850d9bc2c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -3798,7 +3798,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 				reg = 0x78;
 				val = Get_NB32_DCT(dev, Channel, reg);
 				val &= ~(0x3ff<<22);
-				val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22);
+				val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22);
 				val &= ~(1<<DqsRcvEnTrain);
 				Set_NB32_DCT(dev, Channel, reg, val);	/* program MaxRdLatency to correspond with current delay*/
 			}
@@ -7391,7 +7391,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
 
 		p = (u8 *) pDCTstat;
 		start = 0;
-		stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]);
+		stop = ((u32) &((struct DCTStatStruc *)0)->CH_D_DIR_B_DQS);
 		for (i = start; i < stop ; i++) {
 			p[i] = 0;
 		}