diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2014-07-27 19:37:31 +0200 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 04:40:27 +0200 |
| commit | 0f92f630556b4bf2e4c0696cae4c2f8e97eda334 (patch) | |
| tree | b97ad7a89a101c4770774035db5e4693043be928 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | 081651b6677c64a5f2861d831822b5f8f3517c21 (diff) | |
Uniformly spell frequency unit symbol as Hz
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 90b7ed33ec..770b663fe9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -248,7 +248,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry * 6. All var MTRRs reset to zero * 7. State of NB_CFG.DisDatMsk set properly on all CPUs - * 8. All CPUs at 2Ghz Speed (unless DQS training is not installed). + * 8. All CPUs at 2GHz Speed (unless DQS training is not installed). * 9. All cHT links at max Speed/Width (unless DQS training is not installed). * * @@ -258,13 +258,13 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * j CL(j) k F(k) * -------------------------- * 0 2.0 - - - * 1 3.0 1 200 Mhz - * 2 4.0 2 266 Mhz - * 3 5.0 3 333 Mhz - * 4 6.0 4 400 Mhz - * 5 7.0 5 533 Mhz - * 6 8.0 6 667 Mhz - * 7 9.0 7 800 Mhz + * 1 3.0 1 200 MHz + * 2 4.0 2 266 MHz + * 3 5.0 3 333 MHz + * 4 6.0 4 400 MHz + * 5 7.0 5 533 MHz + * 6 8.0 6 667 MHz + * 7 9.0 7 800 MHz */ u8 Node, NodesWmem; u32 node_sys_base; @@ -487,9 +487,9 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, * when 400, 533, 667, it will support dimm0/1/2/3, * and set conf for dimm0, hw will copy to dimm1/2/3 * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800Mhz and above + * Rev A/B only support DIMM0/1 when 800MHz and above * + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800Mhz and above + * Rev C support DIMM0/1/2/3 when 800MHz and above * + 0x100 to next dimm */ for (DIMM = 0; DIMM < 4; DIMM++) { |