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| author | Marc Jones <marc.jones@se-eng.com> | 2012-02-21 17:06:40 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-03-02 23:35:26 +0100 |
| commit | 067d22340c68d21f0dd5a33cf02701bc54005a0d (patch) | |
| tree | 36c9dab29b3ef4884dcc9b0d356c70714f1036c5 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | 07408e687ce440bf665cd6d04d65075b20db0215 (diff) | |
Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.
Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a2e9..d126a95105 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); return; fatalexit: |