diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-26 00:17:10 -0500 |
|---|---|---|
| committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-11-14 23:44:08 +0100 |
| commit | 0d0375b3c6c032759aac23d893dae53242c315e2 (patch) | |
| tree | f61466d07f97dda15f7efd6cceb86cac41a976a5 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | 6b6c653ce7313d137c4f4f86e2e7678f2c19862d (diff) | |
northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12008
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index e098d7f527..1312b34bce 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5631,7 +5631,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { + printk(BIOS_DEBUG, "%s: Start\n", __func__); + mct_ProgramODT_D(pMCTstat, pDCTstat, dct); + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, @@ -5641,6 +5645,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, u32 dword; u32 dev = pDCTstat->dev_dct; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + /* FIXME * Mainboards need to be able to specify the maximum number of DIMMs installable per channel * For now assume a maximum of 2 DIMMs per channel can be installed @@ -5955,6 +5961,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2); } } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, |