diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 10:25:41 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 16:49:15 +0200 |
commit | e1606731b63bedd12398acb57a115aa5d280811e (patch) | |
tree | 8da66e35adfc3142ae1eb822899abf039c975432 /src/northbridge/amd/amdmct/mct/mctsrc2p.c | |
parent | 8aa20193a6dc12ba6cf740b1ad41023475d69698 (diff) |
northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctsrc2p.c')
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index bd3c503097..c7c92acb17 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -62,7 +62,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, bn = 8; // print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel); // print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver); - for ( i=0;i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; // print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); // print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); @@ -100,7 +100,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; // p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; - for (i=0; i<bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -120,7 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for (i=0; i < bn; i++) { + for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ //val += Pass1MemClkDly; |