diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 10:25:41 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 16:49:15 +0200 |
| commit | e1606731b63bedd12398acb57a115aa5d280811e (patch) | |
| tree | 8da66e35adfc3142ae1eb822899abf039c975432 /src/northbridge/amd/amdmct/mct/mctgr.c | |
| parent | 8aa20193a6dc12ba6cf740b1ad41023475d69698 (diff) | |
northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctgr.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctgr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c index a13d4e2f0f..41a479b21e 100644 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ b/src/northbridge/amd/amdmct/mct/mctgr.c @@ -31,12 +31,12 @@ u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct, DramTimingLo = val; /* Dram Timing Low (owns Clock Enable bits) */ NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off); - if (mctGet_NVbits(NV_AllMemClks)==0) { + if (mctGet_NVbits(NV_AllMemClks) == 0) { /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ if (!(pDCTstat->Status & (1<<SB_DiagClks))) { - for (i=0; i<MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { val = Tab_GRCLKDis[i]; - if (val<8) { + if (val < 8) { if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { /* disable memclk */ NewDramTimingLo |= (1<<(i+1)); |