diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:36:02 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:28:51 +0200 |
| commit | 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (patch) | |
| tree | 8d51ad99d2d9469f195694b29a571facf18d89f8 /src/northbridge/amd/amdmct/mct/mctgr.c | |
| parent | 2b010b8795de84b6753c5e49d6a73c25fee96da1 (diff) | |
northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctgr.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctgr.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c index 01d729d701..a13d4e2f0f 100644 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ b/src/northbridge/amd/amdmct/mct/mctgr.c @@ -31,13 +31,13 @@ u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct, DramTimingLo = val; /* Dram Timing Low (owns Clock Enable bits) */ NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off); - if(mctGet_NVbits(NV_AllMemClks)==0) { + if (mctGet_NVbits(NV_AllMemClks)==0) { /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ - if(!(pDCTstat->Status & (1<<SB_DiagClks))) { - for(i=0; i<MAX_DIMMS_SUPPORTED; i++) { + if (!(pDCTstat->Status & (1<<SB_DiagClks))) { + for (i=0; i<MAX_DIMMS_SUPPORTED; i++) { val = Tab_GRCLKDis[i]; - if(val<8) { - if(!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { + if (val<8) { + if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { /* disable memclk */ NewDramTimingLo |= (1<<(i+1)); } @@ -61,7 +61,7 @@ u32 mct_AdjustDramConfigLo_GR(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) ; mov cx,PA_NBMISC+44h ;MCA NB Configuration ; call Get_NB32n_D ; bt eax,22 ;EccEn - ; .if(CARRY?) + ; .if (CARRY?) ; btr eax,BurstLength32 ; .endif */ @@ -72,7 +72,7 @@ u32 mct_AdjustDramConfigLo_GR(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) void mct_AdjustMemHoist_GR(struct DCTStatStruc *pDCTstat, u32 base, u32 HoleSize) { u32 val; - if(base >= pDCTstat->DCTHoleBase) { + if (base >= pDCTstat->DCTHoleBase) { u32 dev = pDCTstat->dev_dct; base += HoleSize; base >>= 27 - 8; |