No warnings day, next round.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 13 insertions, 6 deletions

diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 8b1b0a0af1..661e5f348e 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -520,6 +520,8 @@ struct sys_info {
 
 #include <reset.h>
 
+#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
+	((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
@@ -585,5 +587,6 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 	}
 
 }
+#endif
 
 #endif /* AMDK8_F_H */
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 1b40eb1381..18b3109cf6 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -110,7 +110,7 @@ static void misc_control_init(struct device *dev)
 {
 	uint32_t cmd, cmd_ref;
 	int needs_reset;
-	struct device *f0_dev, *f2_dev;
+	struct device *f0_dev;
 	
 	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
@@ -161,6 +161,7 @@ static void misc_control_init(struct device *dev)
 		}
 	}
 	else if(is_cpu_pre_d0()) {
+		struct device *f2_dev;
 		uint32_t dcl;
 		f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
 		/* Errata 98 
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index b02e9a0058..577e7fd4bb 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -18,10 +18,6 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#if defined (__GNUC__)
-static void hard_reset(void);
-#endif
-
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index e34187154c..cac9f80097 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -707,12 +707,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	printk(BIOS_SPEW, "done.\n");
 }
 
+#if 0
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	return dcl & DCL_Width128;
 }
+#endif
 
 static int is_opteron(const struct mem_controller *ctrl)
 {
@@ -727,6 +729,7 @@ static int is_opteron(const struct mem_controller *ctrl)
 	return !!(nbcap & NBCAP_128Bit);
 }
 
+#if 0
 static int is_registered(const struct mem_controller *ctrl)
 {
 	/* Test to see if we are dealing with registered SDRAM.
@@ -737,7 +740,7 @@ static int is_registered(const struct mem_controller *ctrl)
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	return !(dcl & DCL_UnBuffDimm);
 }
-
+#endif
 
 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 {
@@ -2481,6 +2484,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
 static void set_SlowAccessMode(const struct mem_controller *ctrl)
 {
 	uint32_t dch;
@@ -2491,6 +2495,7 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl)
 
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
+#endif
 
 /*
 	DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 3372474ac5..5cd6d53688 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1872,6 +1872,7 @@ static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 	return pos;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 {
 	/* 30 bytes per channel */
@@ -1902,6 +1903,7 @@ static void dqs_save_MC_NVRAM(unsigned int dev)
 	reg = pci_read_config32(dev, DRAM_CONFIG_HIGH);
 	pos = s3_save_nvram_early(reg, 4, pos);
 }
+#endif
 
 static void dqs_restore_MC_NVRAM(unsigned int dev)
 {