Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 45 insertions, 45 deletions

diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 580f27831b..283e32e235 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -87,7 +87,7 @@
 #define DRAM_TIMING_LOW	   0x88
 #define	 DTL_TCL_SHIFT	   0
 #define	 DTL_TCL_MASK	   7
-#define	  DTL_TCL_BASE 	   1 
+#define	  DTL_TCL_BASE 	   1
 #define	  DTL_TCL_MIN	   3
 #define	  DTL_TCL_MAX	   6
 #define	 DTL_TRCD_SHIFT	   4
@@ -125,7 +125,7 @@
 #define   DTL_TRRD_BASE    2
 #define   DTL_TRRD_MIN	   2
 #define   DTL_TRRD_MAX     5
-#define  DTL_MemClkDis_SHIFT 24    /* Channel A */ 
+#define  DTL_MemClkDis_SHIFT 24    /* Channel A */
 #define  DTL_MemClkDis3       (1 << 26)
 #define  DTL_MemClkDis2       (1 << 27)
 #define  DTL_MemClkDis1       (1 << 28)
@@ -135,16 +135,16 @@
 #define  DTL_MemClkDis0_S1g1      (0xa2 << 24)
 
 /* DTL_MemClkDis for m2 and s1g1 is different */
- 
+
 #define DRAM_TIMING_HIGH   0x8c
 #define  DTH_TRWTTO_SHIFT  4
 #define  DTH_TRWTTO_MASK   7
-#define   DTH_TRWTTO_BASE   2 
+#define   DTH_TRWTTO_BASE   2
 #define   DTH_TRWTTO_MIN    2
 #define   DTH_TRWTTO_MAX    9
 #define	 DTH_TWTR_SHIFT	   8
 #define	 DTH_TWTR_MASK	   3
-#define	  DTH_TWTR_BASE	   0 
+#define	  DTH_TWTR_BASE	   0
 #define	  DTH_TWTR_MIN	   1
 #define	  DTH_TWTR_MAX	   3
 #define	 DTH_TWRRD_SHIFT   10
@@ -154,7 +154,7 @@
 #define	  DTH_TWRRD_MAX	   3
 #define  DTH_TWRWR_SHIFT   12
 #define  DTH_TWRWR_MASK    3
-#define   DTH_TWRWR_BASE   1 
+#define   DTH_TWRWR_BASE   1
 #define   DTH_TWRWR_MIN    1
 #define   DTH_TWRWR_MAX    3
 #define  DTH_TRDRD_SHIFT   14
@@ -167,7 +167,7 @@
 #define	  DTH_TREF_7_8_US  2
 #define	  DTH_TREF_3_9_US  3
 #define  DTH_TRFC0_SHIFT   20 /* for Logical DIMM0 */
-#define  DTH_TRFC_MASK      7  
+#define  DTH_TRFC_MASK      7
 #define	  DTH_TRFC_75_256M   0
 #define	  DTH_TRFC_105_512M  1
 #define   DTH_TRFC_127_5_1G  2
@@ -185,12 +185,12 @@
 #define   DCL_DramTerm_No   0
 #define   DCL_DramTerm_75_OH 1
 #define   DCL_DramTerm_150_OH 2
-#define   DCL_DramTerm_50_OH 3     
+#define   DCL_DramTerm_50_OH 3
 #define  DCL_DrvWeak	   (1<<7)
 #define  DCL_ParEn	   (1<<8)
 #define  DCL_SelfRefRateEn (1<<9)
 #define  DCL_BurstLength32 (1<<10)
-#define  DCL_Width128	   (1<<11) 
+#define  DCL_Width128	   (1<<11)
 #define  DCL_X4Dimm_SHIFT  12
 #define  DCL_X4Dimm_MASK   0xf
 #define  DCL_UnBuffDimm    (1<<16)
@@ -312,7 +312,7 @@
 #define  DATC_CkeFineDelay_MASK  0x1f
 #define   DATC_CkeFineDelay_BASE 0
 #define   DATC_CkeFineDelay_MIN  0
-#define   DATC_CkeFineDelay_MAX 31 
+#define   DATC_CkeFineDelay_MAX 31
 #define  DATC_CkeSetup	(1<<5)
 #define  DATC_CsOdtFineDelay_SHIFT 8
 #define  DATC_CsOdtFineDelay_MASK  0x1f
@@ -320,7 +320,7 @@
 #define   DATC_CsOdtFineDelay_MIN  0
 #define   DATC_CsOdtFineDelay_MAX 31
 #define  DATC_CsOdtSetup   (1<<13)
-#define  DATC_AddrCmdFineDelay_SHIFT 16 
+#define  DATC_AddrCmdFineDelay_SHIFT 16
 #define  DATC_AddrCmdFineDelay_MASK  0x1f
 #define   DATC_AddrCmdFineDelay_BASE 0
 #define   DATC_AddrCmdFineDelay_MIN  0
@@ -361,7 +361,7 @@
 #define DRAM_DQS_RECV_ENABLE_TIME2 0x16
 #define DRAM_DQS_RECV_ENABLE_TIME3 0x19
 
-/* there are index        0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 
+/* there are index        0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39
 that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19
 */
 #define DRAM_CTRL_MISC 0xa0
@@ -417,7 +417,7 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10,
 #define	  SCRUB_655_4us	   15
 #define	  SCRUB_1_31ms	   16
 #define	  SCRUB_2_62ms	   17
-#define	  SCRUB_5_24ms	   18 
+#define	  SCRUB_5_24ms	   18
 #define	  SCRUB_10_49ms	   19
 #define	  SCRUB_20_97ms	   20
 #define	  SCRUB_42ms	   21
@@ -530,7 +530,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 	unsigned needs_reset = 0;
 
 
-	if(sysinfo->nodes == 1) return; // in case only one cpu installed	
+	if(sysinfo->nodes == 1) return; // in case only one cpu installed
 
 	for(i=1; i<sysinfo->nodes; i++) {
 		/* Skip everything if I don't have any memory on this controller */
@@ -563,7 +563,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
 #else
-		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -581,7 +581,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 		print_debug("mem trained failed\n");
 		soft_reset();
 #else
-		printk(BIOS_DEBUG, "mem trained failed\n"); 
+		printk(BIOS_DEBUG, "mem trained failed\n");
 		hard_reset();
 #endif
 	}
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index e42158d92a..13c72fe846 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -56,7 +56,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 
 		printk(BIOS_DEBUG, "before resume errata #%d\n",
 			     (is_post_rev_g) ? 270 : 125);
-		/* 
+		/*
 		   1. Restore memory controller registers as normal.
 		   2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only)
 		   3. Set the EnDramInit bit (Dev:2x7C[31]), clear all other bits in the same register).
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 18b3109cf6..5d51f036cb 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -4,7 +4,7 @@
  * devices which is done by the kernel
  *
  * written in 2003 by Eric Biederman
- * 
+ *
  *  - Athlon64 workarounds by Stefan Reinauer
  *  - "reset once" logic by Yinghai Lu
  */
@@ -24,7 +24,7 @@
 /**
  * @brief Read resources for AGP aperture
  *
- * @param 
+ * @param
  *
  * There is only one AGP aperture resource needed. The resoruce is added to
  * the northbridge of BSP.
@@ -64,7 +64,7 @@ static void mcf3_read_resources(device_t dev)
 static void set_agp_aperture(device_t dev)
 {
 	struct resource *resource;
-		
+
 	resource = probe_resource(dev, 0x94);
 	if (resource) {
 		device_t pdev;
@@ -78,7 +78,7 @@ static void set_agp_aperture(device_t dev)
 
 		/* Get the base address */
 		gart_base = ((resource->base) >> 25) & 0x00007fff;
-		
+
 		/* Update the other northbriges */
 		pdev = 0;
 		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
@@ -90,7 +90,7 @@ static void set_agp_aperture(device_t dev)
 
 			/* Don't set the GART Table base address */
 			pci_write_config32(pdev, 0x98, 0);
-			
+
 			/* Report the resource has been stored... */
 			report_resource_stored(pdev, resource, " <gart>");
 		}
@@ -111,7 +111,7 @@ static void misc_control_init(struct device *dev)
 	uint32_t cmd, cmd_ref;
 	int needs_reset;
 	struct device *f0_dev;
-	
+
 	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
 
@@ -125,7 +125,7 @@ static void misc_control_init(struct device *dev)
 	if (is_cpu_pre_c0()) {
 
 		/* Errata 58
-		 * Disable CPU low power states C2, C1 and throttling 
+		 * Disable CPU low power states C2, C1 and throttling
 		 */
 		cmd = pci_read_config32(dev, 0x80);
 		cmd &= ~(1<<0);
@@ -136,7 +136,7 @@ static void misc_control_init(struct device *dev)
 		pci_write_config32(dev, 0x84, cmd );
 
 		/* Errata 66
-		 * Limit the number of downstream posted requests to 1 
+		 * Limit the number of downstream posted requests to 1
 		 */
 		cmd = pci_read_config32(dev, 0x70);
 		if ((cmd & (3 << 0)) != 2) {
@@ -164,7 +164,7 @@ static void misc_control_init(struct device *dev)
 		struct device *f2_dev;
 		uint32_t dcl;
 		f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
-		/* Errata 98 
+		/* Errata 98
 		 * Set Clk Ramp Hystersis to 7
 		 * Clock Power/Timing Low
 		 */
@@ -192,7 +192,7 @@ static void misc_control_init(struct device *dev)
 			reg = 0x98 + (link * 0x20);
 			link_type = pci_read_config32(f0_dev, reg);
 			/* Only handle coherent link here please */
-			if ((link_type & (LinkConnected|InitComplete|NonCoherent)) 
+			if ((link_type & (LinkConnected|InitComplete|NonCoherent))
 				== (LinkConnected|InitComplete))
 			{
 				cmd &= ~(0xff << (link *8));
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index ad257d0ed6..7ad1b8004c 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -567,7 +567,7 @@ static int is_opteron(const struct mem_controller *ctrl)
 {
 	/* Test to see if I am an Opteron.  Socket 939 based Athlon64
 	 * have dual channel capability, too, so we need a better test
-	 * for Opterons. 
+	 * for Opterons.
 	 * However, all code uses is_opteron() to find out whether to
 	 * use dual channel, so if we really check for opteron here, we
 	 * need to fix up all code using this function, too.
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 6872883416..b89aa38d6a 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -393,7 +393,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	 *	   110 = 8 bus clocks
 	 *	   111 = 9 bus clocks
 	 * [ 7: 7] Reserved
-	 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, 
+	 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
 	 * minium write-to-read delay when both access the same chip select)
 	 *	   00 = Reserved
 	 *	   01 = 1 bus clocks
@@ -525,7 +525,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	 *	       registered DIMM is present
 	 * [19:19] Reserved
 	 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
-	 *	   0 = DRAM address and control signals are driven for one 
+	 *	   0 = DRAM address and control signals are driven for one
 	 *	       MEMCLK cycle
 	 *	   1 = One additional MEMCLK of setup time is provided on all
 	 *	       DRAM address and control signals except CS, CKE, and ODT;
@@ -720,7 +720,7 @@ static int is_opteron(const struct mem_controller *ctrl)
 {
 	/* Test to see if I am an Opteron. M2 and S1G1 support dual
 	 * channel, too, but only support unbuffered DIMMs so we need a
-	 * better test for Opterons. 
+	 * better test for Opterons.
 	 * However, all code uses is_opteron() to find out whether to
 	 * use dual channel, so if we really check for opteron here, we
 	 * need to fix up all code using this function, too.
@@ -1221,7 +1221,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
 			csbase = value;
 			canidate = index;
 		}
-		
+
 		/* See if I have found a new canidate */
 		if (csbase == 0) {
 			break;
@@ -1640,7 +1640,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
 	  /*15*/   200, 160, 120, 100,
 	};
 
-	
+
 	int index;
 	msr_t msr;
 
@@ -1659,7 +1659,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
 		unsigned fid_start;
 		msr = rdmsr(0xc0010015);
 		fid_start = (msr.lo & (0x3f << 24));
-		
+
 		index = fid_start>>25;
 	}
 
@@ -1843,7 +1843,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 				continue;
 			}
 		}
-		
+
 	}
 	/* Make a second pass through the dimms and disable
 	 * any that cannot support the selected memclk and cas latency.
@@ -2060,7 +2060,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
 	if (clocks < TT_MIN) {
 		clocks = TT_MIN;
 	}
-	
+
 	if (clocks > TT_MAX) {
 		printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
 		clocks = TT_MAX;
@@ -3001,7 +3001,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 #else
 	int suspend = 0;
 #endif
- 
+
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 	 unsigned cpu_f0_f1[8];
 	/* FIXME: How about 32 node machine later? */
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 7b453bfc09..c56e51deb0 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -436,7 +436,7 @@ static uint16_t get_exact_T1000(unsigned i)
 		unsigned fid_start;
 		msr = rdmsr(0xc0010015);
 		fid_start = (msr.lo & (0x3f << 24));
-		
+
 		index = fid_start>>25;
 	}
 
@@ -600,12 +600,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
 	}
 
 	for ( ; (channel < 2) && (!Errors); channel++)
-	{ 
-		print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); 
-		
-		/* for each rank */ 
-		/* there are four recriver pairs, loosely associated with CS */ 
-		for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) 
+	{
+		print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1);
+
+		/* for each rank */
+		/* there are four recriver pairs, loosely associated with CS */
+		for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
 		{
 
 			unsigned index=(receiver>>1) * 3 + 0x10;
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index 042bc9949b..82622cdc4c 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -231,7 +231,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max)
 		unsigned where;
 		unsigned long reg;
 #if 0
-		prink(BIOS_DEBUG, "%08x <-  %08x\n", 
+		prink(BIOS_DEBUG, "%08x <-  %08x\n",
 			register_values[i], register_values[i+2]);
 #endif
 		where = register_values[i];