diff options
| author | Myles Watson <mylesgw@gmail.com> | 2008-10-02 19:20:22 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2008-10-02 19:20:22 +0000 |
| commit | d61ada6555ed2e8b5693b987faae1624ec4cbde6 (patch) | |
| tree | 2fe4ea1d9430e69c079c710d56bab2fe3fbaf9cb /src/northbridge/amd/amdk8/resourcemap.c | |
| parent | 7f3d48c9afd8f3397f7ce85148d802082ccc9de9 (diff) | |
Whitespace cleanup (trivial).
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/resourcemap.c')
| -rw-r--r-- | src/northbridge/amd/amdk8/resourcemap.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdk8/resourcemap.c b/src/northbridge/amd/amdk8/resourcemap.c index 4b6833204c..0bae190a73 100644 --- a/src/northbridge/amd/amdk8/resourcemap.c +++ b/src/northbridge/amd/amdk8/resourcemap.c @@ -139,7 +139,7 @@ static void setup_default_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -195,7 +195,7 @@ static void setup_default_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -203,7 +203,7 @@ static void setup_default_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, |