- 1.1.4

  Major restructuring of hypertransport handling.
  Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
  Updates to hard_reset handling when resetting because of the need to change hypertransport link
    speeds and widths.
    (a) No longer assume the boot is good just because we get to a hard reset point.
    (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
       boot counter.
  Updates to arima/hdama mptable so it tracks the new bus numbers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 24 insertions, 19 deletions

diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index ab48f9830e..9105324f33 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -9,29 +9,26 @@
 
 static int cpu_init_detected(void)
 {
-	unsigned long dcl;
-	int cpu_init;
+	unsigned long htic;
+	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+
+	return !!(htic & HTIC_INIT_Detect);
+}
 
+static int bios_reset_detected(void)
+{
 	unsigned long htic;
+	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+
+	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
+}
 
+static int cold_reset_detected(void)
+{
+	unsigned long htic;
 	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
-#if 0
-	print_debug("htic: ");
-	print_debug_hex32(htic);
-	print_debug("\r\n");
-
-	if (!(htic & HTIC_ColdR_Detect)) {
-		print_debug("Cold Reset.\r\n");
-	}
-	if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
-		print_debug("BIOS generated Reset.\r\n");
-	}
-	if (htic & HTIC_INIT_Detect) {
-		print_debug("Init event.\r\n");
-	}
-#endif
-	cpu_init = (htic & HTIC_INIT_Detect);
-	return cpu_init;
+
+	return !(htic & HTIC_ColdR_Detect);
 }
 
 static void distinguish_cpu_resets(unsigned node_id)
@@ -43,3 +40,11 @@ static void distinguish_cpu_resets(unsigned node_id)
 	htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
 	pci_write_config32(device, HT_INIT_CONTROL, htic);
 }
+
+static void set_bios_reset(void)
+{
+	unsigned long htic;
+	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+	htic &= ~HTIC_BIOSR_Detect;
+	pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+}