diff options
author | Martin Roth <martinroth@google.com> | 2016-01-15 10:20:11 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-02-02 14:37:09 +0100 |
commit | 2f91403303a66c5e724761a74863e3452291b154 (patch) | |
tree | 7269f212612416f263dfba9a50f88befe2015d70 /src/northbridge/amd/amdk8/raminit_f_dqs.c | |
parent | bda8a04b0105f2b097b07fa336891af6981541cb (diff) |
src: Fix various spelling and whitespace issues.
This fixes some spelling and whitespace issues that I came across
while working on various things in the tree.
There are no functional changes.
Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdk8/raminit_f_dqs.c')
-rw-r--r-- | src/northbridge/amd/amdk8/raminit_f_dqs.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 23ec60dac8..0b777d18ac 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -585,7 +585,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); /* for each rank */ - /* there are four recriver pairs, loosely associated with CS */ + /* there are four receiver pairs, loosely associated with CS */ for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { @@ -664,14 +664,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st /* FIXME: 64bit MUX */ if(is_Width128) { - /* Program current Receiver enable delay chaannel b */ + /* Program current Receiver enable delay channel b */ pci_write_config32_index_wait(ctrl->f2, 0x98, index+ 0x20, RcvrEnDly); } /* Program the MaxAsyncLat filed with the current DQS receiver enable setting plus 6ns */ - /*Porgram MaxAsyncLat to correspond with current delay */ + /* Program MaxAsyncLat to correspond with current delay */ SetMaxAL_RcvrDly(ctrl, RcvrEnDly); CurrTest = DQS_FAIL; @@ -688,7 +688,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st if(Test0 == DQS_PASS) { Read1LTestPattern(TestAddr0B); - Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr0B); ResetDCTWrPtr(ctrl); @@ -755,7 +755,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st } if(Pass == DQS_FIRST_PASS) { - // We need a better value for DQSPos trainning + // We need a better value for DQSPos training RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */; } else { RcvrEnDly = RcvrEnDlyRmin; @@ -1641,7 +1641,7 @@ static void set_var_mtrr_dqs( } -/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ +/* fms: find most significant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { int r; @@ -1653,7 +1653,7 @@ static inline unsigned int fms(unsigned int x) return r; } -/* fls: find least sigificant bit set */ +/* fls: find least significant bit set */ static inline unsigned int fls(unsigned int x) { int r; |