diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-22 11:42:32 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-22 11:42:32 +0000 |
commit | c02b4fc9db3c3c1e263027382697b566127f66bb (patch) | |
tree | 11bd18488e360e5c1beeb9ccb852ef4489c3689a /src/northbridge/amd/amdk8/raminit_f_dqs.c | |
parent | 27852aba6787617ca5656995cbc7e8ef0a3ea22c (diff) |
printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/raminit_f_dqs.c')
-rw-r--r-- | src/northbridge/amd/amdk8/raminit_f_dqs.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 6ff7a95044..89ccf907cb 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -25,7 +25,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk_debug("%s%x\r\n", str, val); + printk(BIOS_DEBUG, "%s%x\r\n", str, val); } #endif } @@ -34,7 +34,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2); + printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2); } #endif } @@ -43,14 +43,14 @@ static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); } @@ -854,7 +854,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st #if CONFIG_MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ - printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay); + printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif return (CTLRMaxDelay==0xae)?1:0; @@ -1130,7 +1130,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3); - printk_debug("TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); + printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); for(DQSDelay=0; DQSDelay<48; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) @@ -1403,7 +1403,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); - printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a); + printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a); Errors = 0; channel = 0; @@ -1537,7 +1537,7 @@ static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info { print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); + printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); return 1; } else { @@ -1700,7 +1700,7 @@ static unsigned int range_to_mtrr(unsigned int reg, } sizek = 1 << align; #if CONFIG_MEM_TRAIN_SEQ != 1 - printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", + printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") @@ -1895,7 +1895,7 @@ static void dqs_save_MC_NVRAM(unsigned int dev) { int pos = 0; u32 reg; - printk_debug("DQS SAVE NVRAM: %x\n", dev); + printk(BIOS_DEBUG, "DQS SAVE NVRAM: %x\n", dev); pos = dqs_save_MC_NVRAM_ch(dev, 0, pos); pos = dqs_save_MC_NVRAM_ch(dev, 1, pos); /* save the maxasync lat here */ @@ -1908,7 +1908,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev) int pos = 0; u32 reg; - printk_debug("DQS RESTORE FROM NVRAM: %x\n", dev); + printk(BIOS_DEBUG, "DQS RESTORE FROM NVRAM: %x\n", dev); pos = dqs_load_MC_NVRAM_ch(dev, 0, pos); pos = dqs_load_MC_NVRAM_ch(dev, 1, pos); /* load the maxasync lat here */ @@ -1950,9 +1950,9 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i); + printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - printk_debug(" done\r\n"); + printk(BIOS_DEBUG, " done\r\n"); } tsc[1] = rdtsc(); @@ -1968,9 +1968,9 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - printk_debug("DQS Training:DQSPos: %02x\n", i); + printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); if(train_DqsPos(ctrl+i, sysinfo)) goto out; - printk_debug(" done\r\n"); + printk(BIOS_DEBUG, " done\r\n"); } tsc[3] = rdtsc(); @@ -1981,9 +1981,9 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue; - printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i); + printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - printk_debug(" done\r\n"); + printk(BIOS_DEBUG, " done\r\n"); sysinfo->mem_trained[i]=1; dqs_save_MC_NVRAM((ctrl+i)->f2); } @@ -2025,7 +2025,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info if(v) { tsc[0] = rdtsc(); - printk_debug("set DQS timing:RcvrEn:Pass1: %02x\n", i); + printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass1: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { sysinfo->mem_trained[i]=0x81; // @@ -2033,9 +2033,9 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk_debug(" done\r\n"); + printk(BIOS_DEBUG, " done\r\n"); tsc[1] = rdtsc(); - printk_debug("set DQS timing:DQSPos: %02x\n", i); + printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i); } if(train_DqsPos(ctrl, sysinfo)) { @@ -2044,10 +2044,10 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk_debug(" done\r\n"); + printk(BIOS_DEBUG, " done\r\n"); tsc[2] = rdtsc(); - printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i); + printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); } if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // @@ -2055,7 +2055,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk_debug(" done\r\n"); + printk(BIOS_DEBUG, " done\r\n"); tsc[3] = rdtsc(); } @@ -2106,7 +2106,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 - printk_debug("CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); + printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); #else /* Can copy dqs_timing to ap cache and run from cache? |