diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 21:05:26 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:28:48 +0200 |
| commit | 15279a9696c70b82c2223264a505da9122f9aa7b (patch) | |
| tree | 7038d85ab02e392f86a618c49f3db31e14d250f0 /src/northbridge/amd/amdk8/raminit_f.c | |
| parent | 585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (diff) | |
src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdk8/raminit_f.c')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit_f.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index cd4b9fbf52..8ed0335703 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1054,7 +1054,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1460,7 +1460,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; |