diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 20:46:15 +0000 |
---|---|---|
committer | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 20:46:15 +0000 |
commit | d4b278c02c1da92219ebeb34204b9768934aeca3 (patch) | |
tree | 488d097cac9744cfc9b8ff7c89ce69bcb21370cb /src/northbridge/amd/amdk8/amdk8.h | |
parent | 2e3757d11c565a8fe68dc2a2c34975e98304533c (diff) |
AMD Rev F support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/amdk8.h')
-rw-r--r-- | src/northbridge/amd/amdk8/amdk8.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 7e064af974..56b92a2349 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -2,6 +2,10 @@ #define AMDK8_H +#if K8_REV_F_SUPPORT == 1 + #include "amdk8_f.h" + +#else /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -55,6 +59,7 @@ #define DRAM_CSBASE 0x40 #define DRAM_CSMASK 0x60 #define DRAM_BANK_ADDR_MAP 0x80 + #define DRAM_TIMING_LOW 0x88 #define DTL_TCL_SHIFT 0 #define DTL_TCL_MASK 0x7 @@ -96,6 +101,7 @@ #define DTL_TWR_BASE 2 #define DTL_TWR_MIN 2 #define DTL_TWR_MAX 3 + #define DRAM_TIMING_HIGH 0x8c #define DTH_TWTR_SHIFT 0 #define DTH_TWTR_MASK 0x1 @@ -122,6 +128,7 @@ #define DTH_TWCL_BASE 1 #define DTH_TWCL_MIN 1 #define DTH_TWCL_MAX 2 + #define DRAM_CONFIG_LOW 0x90 #define DCL_DLL_Disable (1<<0) #define DCL_D_DRV (1<<1) @@ -140,7 +147,7 @@ #define DCL_DisInRcvrs (1<<24) #define DCL_BypMax_SHIFT 25 #define DCL_En2T (1<<28) -#define DCL_UpperCSMap (1<<29) + #define DRAM_CONFIG_HIGH 0x94 #define DCH_ASYNC_LAT_SHIFT 0 #define DCH_ASYNC_LAT_MASK 0xf @@ -232,3 +239,5 @@ #define ConnectionPending (1 << 4) #endif + +#endif /* AMDK8_H */ |