northbridge/amd: Improve code formatting

Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

5 files changed, 44 insertions, 44 deletions

diff --git a/src/northbridge/amd/amdht/AsPsNb.c b/src/northbridge/amd/amdht/AsPsNb.c
index e34fa4c7a3..2e6c1038e6 100644
--- a/src/northbridge/amd/amdht/AsPsNb.c
+++ b/src/northbridge/amd/amdht/AsPsNb.c
@@ -43,13 +43,13 @@ u8 getMinNbCOF(void)
 	numOfNode = getNumOfNodeNb();
 
 	/* go through each node for the minimum NbCOF (in multiple of CLKIN/2) */
-	for (i=0; i < numOfNode; i++)
+	for (i = 0; i < numOfNode; i++)
 	{
 		/* stub function for APIC ID virtualization for large MP system later */
 		deviceId = translateNodeIdToDeviceIdNb(i);
 
-		/* read all P-state spec registers for NbDid=1 */
-		for (j=0; j < 5; j++)
+		/* read all P-state spec registers for NbDid = 1 */
+		for (j = 0; j < 5; j++)
 		{
 			AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_4,PS_SPEC_REG+(j*PCI_REG_LEN)), &dtemp); /*F4x1E0 + j*4 */
 			/* get NbDid */
@@ -86,13 +86,13 @@ u8 getMinNbCOF(void)
 					nextNbFid = nextNbFid >> 1; */
 			}
 		}
-		if ( i == 0)
+		if (i == 0)
 			nbFid = nextNbFid;
-		else if ( nbFid > nextNbFid )
+		else if (nbFid > nextNbFid)
 		nbFid = nextNbFid;
 	}
 
-	/* add the base and convert to 100MHz divide by 2 if DID=1 */
+	/* add the base and convert to 100MHz divide by 2 if DID = 1 */
 	if (nbDid)
 		nbFid = (u8) (nbFid + 4);
 	else
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index 64092ffc64..7a15325588 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -120,7 +120,7 @@ void CALLCONV Amdmemcpy(void *pDst, const void *pSrc, u32 length)
 	ASSERT(pDst != NULL);
 	ASSERT(pSrc != NULL);
 
-	while (length--){
+	while (length--) {
 	//	*(((u8*)pDst)++) = *(((u8*)pSrc)++);
 		*((u8*)pDst) = *((u8*)pSrc);
 		pDst++;
@@ -134,7 +134,7 @@ void CALLCONV Amdmemset(void *pBuf, u8 val, u32 length)
 	ASSERT(length <= 32768);
 	ASSERT(pBuf != NULL);
 
-	while (length--){
+	while (length--) {
 		//*(((u8*)pBuf)++) = val;
 		*(((u8*)pBuf)) = val;
 		pBuf++;
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index bfda13d9e7..b4838b44d5 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -671,7 +671,7 @@ static void htDiscoveryFloodFill(sMainData *pDat)
 
 			pDat->TotalLinks++;
 
-			if ( !pDat->sysMatrix[currentNode][token] )
+			if (!pDat->sysMatrix[currentNode][token])
 			{
 				pDat->sysDegree[currentNode]++;
 				pDat->sysDegree[token]++;
@@ -745,8 +745,8 @@ static BOOL isoMorph(u8 i, sMainData *pDat)
 		{
 			for (k = 0; k < nodecnt; k++)
 			{
-				if ( pDat->sysMatrix[j][k] !=
-				   pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]] )
+				if (pDat->sysMatrix[j][k] !=
+				   pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]])
 					return FALSE;
 			}
 		}
@@ -1356,12 +1356,12 @@ static void regangLinks(sMainData *pDat)
 		pDat->PortList[i].SelRegang = FALSE;
 		pDat->PortList[i+1].SelRegang = FALSE;
 
-		if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU))
+		if ((pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU))
 			continue;   /*  Only process CPU to CPU links */
 
 		for (j = i+2; j < pDat->TotalLinks*2; j += 2)
 		{
-			if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) )
+			if ((pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU))
 				continue;   /*  Only process CPU to CPU links */
 
 			if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID)
@@ -1506,7 +1506,7 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat)
 		cbPCBBAUpstreamWidth = 16;
 #endif
 
-		if ( (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU))
+		if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU))
 		{
 			if (pDat->HtBlock->AMD_CB_Cpu2CpuPCBLimits)
 			{
@@ -1639,7 +1639,7 @@ static void hammerSublinkFixup(sMainData *pDat)
 				{
 					if ((loFreq != 7) &&  /* {13, 7} 2400MHz / 1200MHz 2:1 */
 						(loFreq != 4) &&  /* {13, 4} 2400MHz /  600MHz 4:1 */
-						(loFreq != 2) )   /* {13, 2} 2400MHz /  400MHz 6:1 */
+						(loFreq != 2))   /* {13, 2} 2400MHz /  400MHz 6:1 */
 						downgrade = TRUE;
 				}
 				else if (hiFreq == 11)
@@ -1651,19 +1651,19 @@ static void hammerSublinkFixup(sMainData *pDat)
 				{
 					if ((loFreq != 5) &&  /* { 9, 5} 1600MHz /  800MHz 2:1 */
 						(loFreq != 2) &&  /* { 9, 2} 1600MHz /  400MHz 4:1 */
-						(loFreq != 0) )   /* { 9, 0} 1600MHz /  200MHz 8:1 */
+						(loFreq != 0))   /* { 9, 0} 1600MHz /  200MHz 8:1 */
 						downgrade = TRUE;
 				}
 				else if (hiFreq == 7)
 				{
 					if ((loFreq != 4) &&  /* { 7, 4} 1200MHz /  600MHz 2:1 */
-						(loFreq != 0) )   /* { 7, 0} 1200MHz /  200MHz 6:1 */
+						(loFreq != 0))   /* { 7, 0} 1200MHz /  200MHz 6:1 */
 						downgrade = TRUE;
 				}
 				else if (hiFreq == 5)
 				{
 					if ((loFreq != 2) &&  /* { 5, 2}  800MHz /  400MHz 2:1 */
-						(loFreq != 0) )   /* { 5, 0}  800MHz /  200MHz 4:1 */
+						(loFreq != 0))   /* { 5, 0}  800MHz /  200MHz 4:1 */
 						downgrade = TRUE;
 				}
 				else if (hiFreq == 2)
@@ -1807,7 +1807,7 @@ static void tuning(sMainData *pDat)
 	/* For each node, invoke northbridge specific buffer tunings or
 	 * system specific customizations.
 	 */
-	for (i=0; i < pDat->NodesDiscovered + 1; i++)
+	for (i = 0; i < pDat->NodesDiscovered + 1; i++)
 	{
 		if ((pDat->HtBlock->AMD_CB_CustomizeBuffers == NULL)
 		   || !pDat->HtBlock->AMD_CB_CustomizeBuffers(i))
diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h
index ab2dace20c..c9737929a1 100644
--- a/src/northbridge/amd/amdht/h3finit.h
+++ b/src/northbridge/amd/amdht/h3finit.h
@@ -358,7 +358,7 @@ typedef struct {
 	 *
 	 * ---------------------------------------------------------------------------------------
 	 */
-	BOOL (*AMD_CB_CustomizeTrafficDistribution)( void );
+	BOOL (*AMD_CB_CustomizeTrafficDistribution)(void);
 
 
 	/**----------------------------------------------------------------------------------------
@@ -379,7 +379,7 @@ typedef struct {
 	 *
 	 * ---------------------------------------------------------------------------------------
 	 */
-	BOOL (*AMD_CB_CustomizeBuffers)( u8 node );
+	BOOL (*AMD_CB_CustomizeBuffers)(u8 node);
 
 	/**----------------------------------------------------------------------------------------
 	 *
diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
index cbe90e03e2..0d0055b4f6 100644
--- a/src/northbridge/amd/amdht/h3ncmn.c
+++ b/src/northbridge/amd/amdht/h3ncmn.c
@@ -352,11 +352,11 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb)
  *	@param[in]   link      = the link on that Node to examine
  *	@param[in]   *nb       = this northbridge
  *	@return            true - The link has the following status
- *				  linkCon=1,	       Link is connected
- *				  InitComplete=1,      Link initialization is complete
- *				  NC=0,		       Link is coherent
- *				  UniP-cLDT=0,	       Link is not Uniprocessor cLDT
- *				  LinkConPend=0	       Link connection is not pending
+ *				  linkCon = 1,		Link is connected
+ *				  InitComplete = 1,	Link initialization is complete
+ *				  NC = 0,		Link is coherent
+ *				  UniP-cLDT = 0,	Link is not Uniprocessor cLDT
+ *				  LinkConPend = 0	Link connection is not pending
  *				  false- The link has some other status
  *
  *****************************************************************************/
@@ -375,7 +375,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb)
 	/*  FN0_98/A4/C4 = LDT Type Register */
 	AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType);
 
-	/*  Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */
+	/*  Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */
 	return (linkType & HTHOST_TYPE_MASK) ==  HTHOST_TYPE_COHERENT;
 #else
 	return 0;
@@ -612,7 +612,7 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb)
 					CPU_NB_FUNC_03,
 					REG_NB_DOWNCORE_3X190),
 					3, 0, &leveling);
-	for (i=0; i<cores; i++)
+	for (i = 0; i < cores; i++)
 	{
 		if (leveling & ((u32) 1 << i))
 		{
@@ -662,7 +662,7 @@ static u8 fam15GetNumCoresOnNode(u8 node, cNorthBridge *nb)
 					CPU_NB_FUNC_03,
 					REG_NB_DOWNCORE_3X190),
 					31, 0, &leveling);
-	for (i=0; i<cores; i++)
+	for (i = 0; i < cores; i++)
 	{
 		if (leveling & ((u32) 1 << i))
 		{
@@ -1122,11 +1122,11 @@ static u8 readSbLink(cNorthBridge *nb)
  *	@param[in]  link   = the Link on that node to examine
  *	@param[in] *nb = this northbridge
  *	@return   = true - The link has the following status
- *					LinkCon=1,     Link is connected
- *					InitComplete=1,Link initilization is complete
- *					NC=1,          Link is coherent
- *					UniP-cLDT=0,   Link is not Uniprocessor cLDT
- *					LinkConPend=0  Link connection is not pending
+ *					LinkCon = 1,     Link is connected
+ *					InitComplete = 1,Link initilization is complete
+ *					NC = 1,          Link is coherent
+ *					UniP-cLDT = 0,   Link is not Uniprocessor cLDT
+ *					LinkConPend = 0  Link connection is not pending
  *					false- The link has some other status
  *
  * ---------------------------------------------------------------------------------------
@@ -1143,7 +1143,7 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb)
 	/* FN0_98/A4/C4 = LDT Type Register */
 	AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType);
 
-	/* Verify linkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */
+	/* Verify linkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */
 	return (linkType & HTHOST_TYPE_MASK) ==  HTHOST_TYPE_NONCOHERENT;
 }
 
@@ -1922,7 +1922,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *
 			CPU_HTNB_FUNC_00,
 			REG_HT_TRAFFIC_DIST_0X164),
 			23, 16, &links01);
-	/* DstNode = 1, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */
+	/* DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */
 	temp = 0x0107;
 	AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(0),
 			makePCIBusFromNode(0),
@@ -1939,7 +1939,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *
 			CPU_HTNB_FUNC_00,
 			REG_HT_TRAFFIC_DIST_0X164),
 			23, 16, &links10);
-	/* DstNode = 0, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */
+	/* DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */
 	temp = 0x0007;
 	AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(1),
 			makePCIBusFromNode(1),
@@ -2088,13 +2088,13 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
 				makePCIDeviceFromNode(node),
 				CPU_NB_FUNC_03,
 				REG_NB_FIFOPTR_3XDC);
-	for (i=0; i < nb->maxLinks; i++)
+	for (i = 0; i < nb->maxLinks; i++)
 	{
 		temp = 0;
 		if (nb->verifyLinkIsCoherent(node, i, nb))
 		{
 			temp = 0x26;
-			ASSERT(i<3);
+			ASSERT(i < 3);
 			AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp);
 		}
 		else
@@ -2102,7 +2102,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
 			if (nb->verifyLinkIsNonCoherent(node, i, nb))
 			{
 				temp = 0x25;
-				ASSERT(i<3);
+				ASSERT(i < 3);
 				AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp);
 			}
 		}
@@ -2142,7 +2142,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
 			 * Errata 153 applies to JH-1, JH-2 and older.  It is fixed in JH-3
 			 * (and, one assumes, from there on).
 			 */
-			for (i=0; i < (pDat->NodesDiscovered +1); i++)
+			for (i = 0; i < (pDat->NodesDiscovered +1); i++)
 			{
 				AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(i),
 						makePCIBusFromNode(i),
@@ -2158,7 +2158,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
 			}
 		}
 
-		for (i=0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++)
+		for (i = 0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++)
 		{
 			isOuter = FALSE;
 			/* Check for outer node by scanning the config maps on node 0 for one
@@ -2179,7 +2179,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
 				if (node == (u8)temp)
 				{
 					/* This is an outer node.	Tune it appropriately. */
-					for (j=0; j < nb->maxLinks; j++)
+					for (j = 0; j < nb->maxLinks; j++)
 					{
 						if (isErrata153)
 						{
@@ -2218,7 +2218,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
 			if (isErrata153)
 			{
 				/* Tuning for inner node coherent links */
-				for (j=0; j < nb->maxLinks; j++)
+				for (j = 0; j < nb->maxLinks; j++)
 				{
 					if (nb->verifyLinkIsCoherent(node, j, nb))
 					{