diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-08 19:35:06 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-11 18:45:14 +0100 |
| commit | 83abd81c8acb3a53dfc125e248d9e5fd58f3e0f7 (patch) | |
| tree | ca0652a1421652f4eb8b4af358f66e2fc256e1db /src/northbridge/amd/amdht | |
| parent | dd4390b6e055ef862084a5fc45b756d6fe09151d (diff) | |
cpu/amd: Add CC6 support
This patch adds CC6 power save support to the AMD Family 15h
support code. As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.
Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.
Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdht')
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 559c67d990..d4e6a29f42 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -250,7 +251,7 @@ #define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */ -#define NM_PS_REG 5 /* number of P-state MSR registers */ +#define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */ /* sFidVidInit.outFlags defines */ #define PWR_CK_OK 0 /* System board check OK */ |