diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-07 12:16:56 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-09 15:51:10 +0000 |
| commit | 64f6b71af5443ac4e1126dc5f5202a1bc8657b31 (patch) | |
| tree | a9dd78971edaf050f8a215332755b1a0f55d6cf1 /src/northbridge/amd/amdfam10 | |
| parent | bc0ec507f2183e28c9b45c34c46ce93ca070aed6 (diff) | |
src/northbridge: Fix typo
Change-Id: I00094028036f33892362b935899e1bceef1da625
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdfam10')
| -rw-r--r-- | src/northbridge/amd/amdfam10/amdfam10.h | 8 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/resourcemap.c | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index b744e96562..5102b0bb30 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -314,7 +314,7 @@ struct MCTStatStruc; // for 0x98 index and 0x9c data for DCT0 // for 0x198 index and 0x19c data for DCT1 -// even at ganged mode, 0x198/0x19c will be used for channnel B +// even at ganged mode, 0x198/0x19c will be used for channel B #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 #define DCAO_DctOffset_SHIFT 0 @@ -368,9 +368,9 @@ struct MCTStatStruc; #define DODCC_ProcOdt_75_OHMS 2 /* - for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs - for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0 - F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1 + for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs + for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 + F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 So Socket F with Four Logical DIMM will only support DDR2 800 ? */ /* there are index +100 ===> for DIMM1 diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 5db6886e41..362872b261 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -121,7 +121,7 @@ static void setup_default_resource_map(void) * 0 = CPU writes may be posted * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit + * This field defines the upp address bits of a 40-bit * address that defines the end of a memory-mapped * I/O region n */ |