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authorStefan Reinauer <stepan@coresystems.de>2009-06-30 15:17:49 +0000
committerStefan Reinauer <stepan@openbios.org>2009-06-30 15:17:49 +0000
commit0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch)
tree81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/northbridge/amd/amdfam10
parent9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff)
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10')
-rw-r--r--src/northbridge/amd/amdfam10/Config.lb12
-rw-r--r--src/northbridge/amd/amdfam10/amdfam10.h6
-rw-r--r--src/northbridge/amd/amdfam10/amdfam10_acpi.c16
-rw-r--r--src/northbridge/amd/amdfam10/amdfam10_conf.c52
-rw-r--r--src/northbridge/amd/amdfam10/debug.c2
-rw-r--r--src/northbridge/amd/amdfam10/early_ht.c26
-rw-r--r--src/northbridge/amd/amdfam10/get_pci1234.c2
-rw-r--r--src/northbridge/amd/amdfam10/misc_control.c4
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c108
-rw-r--r--src/northbridge/amd/amdfam10/raminit.h4
-rw-r--r--src/northbridge/amd/amdfam10/raminit_amdmct.c4
-rw-r--r--src/northbridge/amd/amdfam10/reset_test.c16
-rw-r--r--src/northbridge/amd/amdfam10/resourcemap.c88
13 files changed, 170 insertions, 170 deletions
diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb
index 4f84115d77..f217fcdd3c 100644
--- a/src/northbridge/amd/amdfam10/Config.lb
+++ b/src/northbridge/amd/amdfam10/Config.lb
@@ -17,19 +17,19 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-uses AGP_APERTURE_SIZE
-uses HAVE_ACPI_TABLES
-uses HAVE_HIGH_TABLES
+uses CONFIG_AGP_APERTURE_SIZE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_HIGH_TABLES
-default AGP_APERTURE_SIZE=0x4000000
-default HAVE_HIGH_TABLES=1
+default CONFIG_AGP_APERTURE_SIZE=0x4000000
+default CONFIG_HAVE_HIGH_TABLES=1
config chip.h
driver northbridge.o
driver misc_control.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
object amdfam10_acpi.o
makerule ssdt.c
depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl"
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index d3fb11e349..4cca443716 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -958,9 +958,9 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#ifdef __ROMCC__
#if NODE_NUMS==64
- #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CBB,(CDB+x),fn)):(PCI_DEV((CBB-1),(CDB+x-32),fn)))
+ #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
- #define NODE_PCI(x, fn) PCI_DEV(CBB,(CDB+x),fn)
+ #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
#endif
#endif
@@ -1025,7 +1025,7 @@ struct nodes_info_t {
//#define MEM_CS_COPY 1
#define MEM_CS_COPY NODE_NUMS
-#if MEM_TRAIN_SEQ == 0
+#if CONFIG_MEM_TRAIN_SEQ == 0
#define DQS_DELAY_COPY NODE_NUMS
#else
// #define DQS_DELAY_COPY 1
diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
index 4651b17157..f902d6ee98 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
@@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned long current)
/* fill the first 8 byte with that num */
/* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
- struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u8 *ln = sysinfox->ln;
@@ -190,7 +190,7 @@ void update_ssdt(void *ssdt)
u8 *CBST;
u8 *CBBX;
u8 *CBS2;
- u8 *CBB2;
+ u8 *CONFIG_CBB2;
int i;
@@ -208,7 +208,7 @@ void update_ssdt(void *ssdt)
HCDN = ssdt+0x57a; //+5 will be next HCDN
CBBX = ssdt+0x61f; //
CBST = ssdt+0x626;
- CBB2 = ssdt+0x62d; //
+ CONFIG_CBB2 = ssdt+0x62d; //
CBS2 = ssdt+0x634;
for(i=0;i<HC_NUMS;i++) {
@@ -245,9 +245,9 @@ void update_ssdt(void *ssdt)
int_to_stream(0x20202020, HCDN + i*5);
}
- *CBBX = (u8)(CBB);
+ *CBBX = (u8)(CONFIG_CBB);
- if(CBB == 0xff) {
+ if(CONFIG_CBB == 0xff) {
*CBST = (u8) (0x0f);
} else {
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
@@ -258,12 +258,12 @@ void update_ssdt(void *ssdt)
}
}
- if((CBB == 0xff) && (sysconf.nodes>32)) {
+ if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
*CBS2 = 0x0f;
- *CBB2 = (u8)(CBB-1);
+ *CONFIG_CBB2 = (u8)(CONFIG_CBB-1);
} else {
*CBS2 = 0x00;
- *CBB2 = 0x00;
+ *CONFIG_CBB2 = 0x00;
}
}
diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c
index f7c6a3d3be..cd958c5216 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -33,12 +33,12 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
device_t dev;
struct dram_base_mask_t d;
#if defined(__ROMCC__)
- dev = PCI_DEV(CBB, CDB, 1);
+ dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
#else
dev = __f1_dev[0];
#endif
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
// I will use ext space only for simple
pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
@@ -65,7 +65,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
{
u32 i;
device_t dev;
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
// I will use ext space only for simple
u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
d_base_i = nodeid | (0<<28);
@@ -94,7 +94,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
dev = __f1_dev[i];
#endif
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
// I will use ext space only for simple
pci_write_config32(dev, 0x110, d_base_i);
pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
@@ -232,7 +232,7 @@ static u32 get_one_DCT(struct mem_info *meminfo)
return one_DCT;
}
#endif
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
{
@@ -316,7 +316,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
#endif
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
u32 busn_min, u32 busn_max,
u32 type)
@@ -388,7 +388,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
busn_min>>=segbit;
busn_max>>=segbit;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index < 4) {
#endif
tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
@@ -400,7 +400,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif
pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
}
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
return;
}
@@ -429,7 +429,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 i;
device_t dev;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index<4) {
#endif
for(i=0; i<nodes; i++) {
@@ -440,7 +440,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif
pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
}
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
return;
}
@@ -458,7 +458,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
}
-#if PCI_BUS_SEGN_BITS
+#if CONFIG_PCI_BUS_SEGN_BITS
static u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
sys_info_conf_t *sysinfo)
{
@@ -488,7 +488,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 tempreg;
device_t dev;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index<4) {
#endif
/* io range allocation */
@@ -510,7 +510,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif
pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
}
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
return;
}
@@ -541,7 +541,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
{
u32 i;
device_t dev;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(ht_c_index<4) {
#endif
/* io range allocation */
@@ -554,7 +554,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
}
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
return;
}
// : if hc_c_index > 3, We should use io_min, io_max to clear extend space
@@ -592,7 +592,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
}
}
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
u32 j;
// clear the extend space
for(j = 0; j< nodes; j++) {
@@ -624,7 +624,7 @@ static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8);
for(ht_c_index=0;ht_c_index<4; ht_c_index++) {
- reg = pci_read_config32(PCI_DEV(CBB, CDB, 1), 0xe0 + ht_c_index * 4);
+ reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4);
if(((reg & 0xffff) == 0x0000)) { /*found free*/
break;
}
@@ -660,7 +660,7 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
static void set_BusSegmentEn(u32 node, u32 segbit)
{
-#if PCI_BUS_SEGN_BITS
+#if CONFIG_PCI_BUS_SEGN_BITS
u32 dword;
device_t dev;
@@ -715,12 +715,12 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 io_min, u32 io_max)
{
u32 val;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(reg!=0x110) {
#endif
/* io range allocation */
index = (reg-0xc0)>>3;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
} else {
index+=4;
}
@@ -740,12 +740,12 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 mmio_min, u32 mmio_max)
{
u32 val;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(reg!=0x110) {
#endif
/* io range allocation */
index = (reg-0x80)>>3;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
} else {
index+=8;
}
@@ -767,7 +767,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 i;
u32 tempreg;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(reg!=0x110) {
#endif
/* io range allocation */
@@ -789,7 +789,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
#endif
for(i=0; i<sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
return;
}
@@ -816,7 +816,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 i;
u32 tempreg;
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
if(reg!=0x110) {
#endif
/* io range allocation */
@@ -826,7 +826,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
for(i=0; i<sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
-#if EXT_CONF_SUPPORT
+#if CONFIG_EXT_CONF_SUPPORT
return;
}
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index a8b93b1818..b0aee4bccc 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -34,7 +34,7 @@ static void print_debug_addr(const char *str, void *val)
static void print_debug_pci_dev(u32 dev)
{
-#if PCI_BUS_SEGN_BITS==0
+#if CONFIG_PCI_BUS_SEGN_BITS==0
printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
#else
printk_debug("PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index 43774ded3e..b1c21f2dd3 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -21,7 +21,7 @@
// mmconf is not ready yet
static void set_bsp_node_CHtExtNodeCfgEn(void)
{
-#if EXT_RT_TBL_SUPPORT == 1
+#if CONFIG_EXT_RT_TBL_SUPPORT == 1
u32 dword;
dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
dword |= (1<<27) | (1<<25);
@@ -34,14 +34,14 @@ static void set_bsp_node_CHtExtNodeCfgEn(void)
/* CHtExtAddrEn */
pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword);
- // CPU on bus 0xff and 0xfe now. For now on we can use CBB and CDB.
+ // CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB.
#endif
}
static void enumerate_ht_chain(void)
{
-#if HT_CHAIN_UNITID_BASE != 0
-/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain),
+#if CONFIG_HT_CHAIN_UNITID_BASE != 0
+/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain),
if so, don't need to go through the chain */
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
@@ -50,16 +50,16 @@ static void enumerate_ht_chain(void)
* links needs to be programed to point at bus 0.
*/
unsigned next_unitid, last_unitid = 0;
-#if HT_CHAIN_END_UNITID_BASE != 0x20
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
// let't record the device of last ht device, So we can set the
- // Unitid to HT_CHAIN_END_UNITID_BASE
+ // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid = 0;
u8 real_last_pos = 0;
int ht_dev_num = 0; // except host_bridge
u8 end_used = 0;
#endif
- next_unitid = HT_CHAIN_UNITID_BASE;
+ next_unitid = CONFIG_HT_CHAIN_UNITID_BASE;
do {
u32 id;
u8 hdr_type, pos;
@@ -99,10 +99,10 @@ static void enumerate_ht_chain(void)
unsigned ctrl, ctrl_off;
device_t devx;
-#if HT_CHAIN_END_UNITID_BASE != 0x20
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if(next_unitid>=0x18) {
if(!end_used) {
- next_unitid = HT_CHAIN_END_UNITID_BASE;
+ next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
} else {
goto out;
@@ -112,7 +112,7 @@ static void enumerate_ht_chain(void)
real_last_pos = pos;
ht_dev_num++ ;
#endif
- #if HT_CHAIN_END_UNITID_BASE == 0
+ #if CONFIG_HT_CHAIN_END_UNITID_BASE == 0
if (!next_unitid)
goto out;
#endif
@@ -161,12 +161,12 @@ static void enumerate_ht_chain(void)
} while(last_unitid != next_unitid);
out: ;
-#if HT_CHAIN_END_UNITID_BASE != 0x20
- if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) {
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+ if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
u16 flags;
flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
- flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
+ flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
}
#endif
diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c
index 1217a8be6b..f6a196aabf 100644
--- a/src/northbridge/amd/amdfam10/get_pci1234.c
+++ b/src/northbridge/amd/amdfam10/get_pci1234.c
@@ -49,7 +49,7 @@
* reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk)
*
* Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c
- * on MB dir. Also, don't forget to increase the ACPI_SSDTX_NUM etc if you have
+ * on MB dir. Also, don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc if you have
* too much SSDT. How about co-processor on socket 1 on 2 way system.
* or socket 2, and socket3 on 4 way system? treat that as one hc too!
*
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index 634fec53ce..a321a656d2 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -59,7 +59,7 @@ static void mcf3_read_resources(device_t dev)
pci_dev_read_resources(dev);
/* If we are not the first processor don't allocate the gart apeture */
- if (dev->path.pci.devfn != PCI_DEVFN(CDB, 3)) {
+ if (dev->path.pci.devfn != PCI_DEVFN(CONFIG_CDB, 3)) {
return;
}
@@ -69,7 +69,7 @@ static void mcf3_read_resources(device_t dev)
if (iommu) {
/* Add a Gart apeture resource */
resource = new_resource(dev, 0x94);
- resource->size = iommu?AGP_APERTURE_SIZE:1;
+ resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1;
resource->align = log2(resource->size);
resource->gran = log2(resource->size);
resource->limit = 0xffffffff; /* 4G */
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 6a9504ccc1..fa7cb6db00 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -42,7 +42,7 @@
#include "amdfam10.h"
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
#include <cpu/amd/model_10xxx_rev.h>
#endif
@@ -60,13 +60,13 @@ device_t get_node_pci(u32 nodeid, u32 fn)
{
#if NODE_NUMS == 64
if(nodeid<32) {
- return dev_find_slot(CBB, PCI_DEVFN(CDB + nodeid, fn));
+ return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
- return dev_find_slot(CBB-1, PCI_DEVFN(CDB + nodeid - 32, fn));
+ return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
#else
- return dev_find_slot(CBB, PCI_DEVFN(CDB + nodeid, fn));
+ return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
#endif
}
@@ -83,7 +83,7 @@ static void get_fx_devs(void)
__f4_dev[i] = get_node_pci(i, 4);
}
if (!__f1_dev[0]) {
- printk_err("Cannot find %02x:%02x.1", CBB, CDB);
+ printk_err("Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
die("Cannot go on\n");
}
}
@@ -113,14 +113,14 @@ static u32 amdfam10_nodeid(device_t dev)
#if NODE_NUMS == 64
unsigned busn;
busn = dev->bus->secondary;
- if(busn != CBB) {
- return (dev->path.pci.devfn >> 3) - CDB + 32;
+ if(busn != CONFIG_CBB) {
+ return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
- return (dev->path.pci.devfn >> 3) - CDB;
+ return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
}
#else
- return (dev->path.pci.devfn >> 3) - CDB;
+ return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
#endif
}
@@ -156,7 +156,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink,
u32 busn = max&0xff;
u32 max_devfn;
-#if HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT==1
if(is_sublink1) {
u32 regpos;
u32 reg;
@@ -187,7 +187,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink,
*/
ht_c_index = get_ht_c_index(nodeid, link, &sysconf);
-#if EXT_CONF_SUPPORT == 0
+#if CONFIG_EXT_CONF_SUPPORT == 0
if(ht_c_index>=4) return max;
#endif
@@ -196,12 +196,12 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink,
* so we set the subordinate bus number to 0xff for the moment.
*/
-#if SB_HT_CHAIN_ON_BUS0 > 0
+#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
// first chain will on bus 0
if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
min_bus = max;
}
- #if SB_HT_CHAIN_ON_BUS0 > 1
+ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
// second chain will be on 0x40, third 0x80, forth 0xc0
// i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0
// >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config.
@@ -295,9 +295,9 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max)
// Put sb chain in bus 0
-#if SB_HT_CHAIN_ON_BUS0 > 0
+#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
if(nodeid==0) {
- #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
+ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
#endif
max = amdfam10_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
@@ -305,18 +305,18 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max)
#endif
-#if PCI_BUS_SEGN_BITS
+#if CONFIG_PCI_BUS_SEGN_BITS
max = check_segn(dev, max, sysconf.nodes, &sysconf);
#endif
for(link = 0; link < dev->links; link++) {
-#if SB_HT_CHAIN_ON_BUS0 > 0
+#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
if( (nodeid == 0) && (sblink == link) ) continue; //already done
#endif
offset_unitid = 0;
- #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
- #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if((nodeid == 0) && (sblink == link))
#endif
offset_unitid = 1;
@@ -434,7 +434,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam10_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
@@ -464,7 +464,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -485,7 +485,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -774,7 +774,7 @@ static u32 find_pci_tolm(struct bus *bus, u32 tolm)
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
#endif
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -786,7 +786,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
struct hw_mem_hole_info mem_hole;
int i;
- mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
+ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
for (i = 0; i < sysconf.nodes; i++) {
@@ -840,7 +840,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int i)
u32 hole_sizek;
u32 one_DCT;
- struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct mem_info *meminfo;
meminfo = &sysinfox->meminfo[i];
@@ -911,7 +911,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int i)
#endif
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
@@ -926,7 +926,7 @@ static void pci_domain_set_resources(device_t dev)
u32 pci_tolm;
int i, idx;
u32 link;
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info mem_hole;
u32 reset_memhole = 1;
#endif
@@ -1003,7 +1003,7 @@ static void pci_domain_set_resources(device_t dev)
/* Round the mmio hold to 64M */
mmio_basek &= ~((64*1024) - 1);
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare
* mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
* use hole_basek as mmio_basek and we don't need to reset hole.
@@ -1023,7 +1023,7 @@ static void pci_domain_set_resources(device_t dev)
if(reset_memhole) {
if(mem_hole.node_id!=-1) {
- /* We need to select HW_MEM_HOLE_SIZEK for raminit, it can not
+ /* We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not
make hole_startk to some basek too!
We need to reset our Mem Hole, because We want more big HOLE
than we already set
@@ -1033,7 +1033,7 @@ static void pci_domain_set_resources(device_t dev)
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
- #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
+ #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
// We need to double check if the mmio_basek is valid for hole
// setting, if it is equal to basek, we need to decrease it some
resource_t basek_pri;
@@ -1089,7 +1089,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
if (i==0 && high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
@@ -1100,9 +1100,9 @@ static void pci_domain_set_resources(device_t dev)
#endif
}
#if CONFIG_AMDMCT == 0
- #if HW_MEM_HOLE_SIZEK != 0
+ #if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole) {
- struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct mem_info *meminfo;
meminfo = &sysinfox->meminfo[i];
sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes);
@@ -1122,7 +1122,7 @@ static void pci_domain_set_resources(device_t dev)
}
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
i, mmio_basek, basek, limitk);
if (i==0 && high_tables_base==0) {
@@ -1150,7 +1150,7 @@ static u32 pci_domain_scan_bus(device_t dev, u32 max)
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
// all nodes
for(i = 0; i< sysconf.nodes; i++) {
int index;
@@ -1164,7 +1164,7 @@ static u32 pci_domain_scan_bus(device_t dev, u32 max)
for(i=0;i<dev->links;i++) {
- max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CDB, 0), 0xff, max);
+ max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CONFIG_CDB, 0), 0xff, max);
}
/* Tune the hypertransport transaction for best performance.
@@ -1197,7 +1197,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
-#if MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
@@ -1228,16 +1228,16 @@ static void sysconf_init(device_t dev) // first node
sysconf.bsp_apicid = lapicid();
sysconf.apicid_offset = sysconf.bsp_apicid;
-#if (ENABLE_APIC_EXT_ID == 1)
+#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
{
sysconf.enabled_apic_ext_id = 1;
}
- #if (APIC_ID_OFFSET>0)
+ #if (CONFIG_APIC_ID_OFFSET>0)
if(sysconf.enabled_apic_ext_id) {
if(sysconf.bsp_apicid == 0) {
/* bsp apic id is not changed */
- sysconf.apicid_offset = APIC_ID_OFFSET;
+ sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
} else {
sysconf.lift_bsp_apicid = 1;
}
@@ -1281,14 +1281,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
nb_cfg_54 = read_nb_cfg_54();
-#if CBB
- dev_mc = dev_find_slot(0, PCI_DEVFN(CDB, 0)); //0x00
+#if CONFIG_CBB
+ dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
if(dev_mc && dev_mc->bus) {
printk_debug("%s found", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
printk_debug("\n%s move to ",dev_path(dev_mc));
- dev_mc->bus->secondary = CBB; // move to 0xff
+ dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
printk_debug("%s",dev_path(dev_mc));
} else {
@@ -1297,7 +1297,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
printk_debug("\n");
}
- dev_mc = dev_find_slot(CBB, PCI_DEVFN(CDB, 0));
+ dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
if(!dev_mc) {
dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
if (dev_mc && dev_mc->bus) {
@@ -1306,7 +1306,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) {
printk_debug("%s move to ",dev_path(dev_mc));
- dev_mc->bus->secondary = CBB; // move to 0xff
+ dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
printk_debug("%s\n",dev_path(dev_mc));
while(dev_mc){
printk_debug("%s move to ",dev_path(dev_mc));
@@ -1321,9 +1321,9 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
#endif
- dev_mc = dev_find_slot(CBB, PCI_DEVFN(CDB, 0));
+ dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
if (!dev_mc) {
- printk_err("%02x:%02x.0 not found", CBB, CDB);
+ printk_err("%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
die("");
}
@@ -1331,7 +1331,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
nodes = sysconf.nodes;
-#if CBB && (NODE_NUMS > 32)
+#if CONFIG_CBB && (NODE_NUMS > 32)
if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe
if(pci_domain->links==1) {
pci_domain->links++; // from 1 to 2
@@ -1340,7 +1340,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
pci_domain->link[1].children = 0;
printk_debug("%s links increase to %d\n", dev_path(pci_domain), pci_domain->links);
}
- pci_domain->link[1].secondary = CBB - 1;
+ pci_domain->link[1].secondary = CONFIG_CBB - 1;
}
#endif
/* Find which cpus are present */
@@ -1351,10 +1351,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
unsigned busn, devn;
struct bus *pbus;
- busn = CBB;
- devn = CDB+i;
+ busn = CONFIG_CBB;
+ devn = CONFIG_CDB+i;
pbus = dev_mc->bus;
-#if CBB && (NODE_NUMS > 32)
+#if CONFIG_CBB && (NODE_NUMS > 32)
if(i>=32) {
busn--;
devn-=32;
@@ -1381,7 +1381,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
*/
int j;
int linknum;
-#if HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT==1
linknum = 8;
#else
linknum = 4;
@@ -1440,7 +1440,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (cpu) {
cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j;
- #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET>0)
+ #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0)
if(sysconf.enabled_apic_ext_id) {
if(sysconf.lift_bsp_apicid) {
cpu->path.apic.apic_id += sysconf.apicid_offset;
diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h
index e446b54e6b..2d3a621b40 100644
--- a/src/northbridge/amd/amdfam10/raminit.h
+++ b/src/northbridge/amd/amdfam10/raminit.h
@@ -21,7 +21,7 @@
#define RAMINIT_H
#if 0
-#if DIMM_SUPPORT==0x0110
+#if CONFIG_DIMM_SUPPORT==0x0110
//FBDIMM REG
/* each channel can have 8 fbdimm */
#define DIMM_SOCKETS 8
@@ -42,7 +42,7 @@ struct mem_controller {
#endif
#endif
-//#if (DIMM_SUPPORT & 0x00ff)==0x0004
+//#if (CONFIG_DIMM_SUPPORT & 0x00ff)==0x0004
//DDR2 REG and unbuffered : Socket F 1027 and AM3
/* every channel have 4 DDR2 DIMM for socket F
* 2 for socket M2/M3
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index fd967b5ebf..3ea22c5e4c 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -84,7 +84,7 @@ int mctRead_SPD(u32 smaddr, u32 reg)
void mctSMBhub_Init(u32 node)
{
- struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
activate_spd_rom(ctrl);
}
@@ -93,7 +93,7 @@ void mctSMBhub_Init(u32 node)
void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
{
int j;
- struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
for(j=0;j<DIMM_SOCKETS;j++) {
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 389d8e60a9..69869bf48c 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -43,7 +43,7 @@ static u32 cpu_init_detected(u8 nodeid)
static u32 bios_reset_detected(void)
{
u32 htic;
- htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
+ htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
}
@@ -51,7 +51,7 @@ static u32 bios_reset_detected(void)
static u32 cold_reset_detected(void)
{
u32 htic;
- htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
+ htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
return !(htic & HTIC_ColdR_Detect);
}
@@ -59,7 +59,7 @@ static u32 cold_reset_detected(void)
static u32 other_reset_detected(void) // other warm reset not started by BIOS
{
u32 htic;
- htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
+ htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect);
}
@@ -91,7 +91,7 @@ static void set_bios_reset(void)
device_t dev;
int i;
- nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1;
+ nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
dev = NODE_PCI(i,0);
@@ -115,7 +115,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
u32 config_map;
- config_map = pci_io_read_config32(PCI_DEV(CBB, CDB, 1), reg);
+ config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg);
if ((config_map & 3) != 3) {
continue;
}
@@ -126,7 +126,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
}
}
-#if EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT == 1
// let's check that in extend space
// use the nodeid extend space to find out the bus for the linkn
u32 tempreg;
@@ -157,8 +157,8 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
static u32 get_sblk(void)
{
u32 reg;
- /* read PCI_DEV(CBB,CDB,0) 0x64 bit [8:9] to find out SbLink m */
- reg = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), 0x64);
+ /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */
+ reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64);
return ((reg>>8) & 3) ;
}
diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c
index 49d546861c..4bfe03cf45 100644
--- a/src/northbridge/amd/amdfam10/resourcemap.c
+++ b/src/northbridge/amd/amdfam10/resourcemap.c
@@ -49,14 +49,14 @@ static void setup_default_resource_map(void)
* This field defines the upper address bits of a 40 bit
* address that define the end of the DRAM region.
*/
- PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
@@ -87,14 +87,14 @@ static void setup_default_resource_map(void)
* This field defines the upper address bits of a 40-bit
* address that define the start of the DRAM region.
*/
- PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
@@ -129,14 +129,14 @@ static void setup_default_resource_map(void)
* address that defines the end of a memory-mapped
* I/O region n
*/
- PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -165,14 +165,14 @@ static void setup_default_resource_map(void)
* address that defines the start of memory-mapped
* I/O region i
*/
- PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -199,10 +199,10 @@ static void setup_default_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
- PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -231,10 +231,10 @@ static void setup_default_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
@@ -274,10 +274,10 @@ static void setup_default_resource_map(void)
* This field defines the highest bus number in
* configuration regin i
*/
- PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0xff000003,
- PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
};
u32 max;