diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-04-30 13:58:42 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-04-30 13:58:42 +0000 |
| commit | b5fb0c5c4eda2329d848aedcf4f7e8b6dc8012b2 (patch) | |
| tree | 9a0897635ecbeab0dd64124cd165d3460174a359 /src/northbridge/amd/amdfam10 | |
| parent | 6841ce653741b3dafe8e3482b4a93adbaee53552 (diff) | |
Add high tables support to all northbridges.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10')
| -rw-r--r-- | src/northbridge/amd/amdfam10/Config.lb | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 23 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb index 5e9081991d..79b7b49280 100644 --- a/src/northbridge/amd/amdfam10/Config.lb +++ b/src/northbridge/amd/amdfam10/Config.lb @@ -19,8 +19,10 @@ uses AGP_APERTURE_SIZE uses HAVE_ACPI_TABLES +uses HAVE_HIGH_TABLES default AGP_APERTURE_SIZE=0x4000000 +default HAVE_HIGH_TABLES=1 config chip.h diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 92f9ea3819..6a9504ccc1 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -911,6 +911,11 @@ static void disable_hoist_memory(unsigned long hole_startk, int i) #endif +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM == 1 @@ -1084,6 +1089,15 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; +#if HAVE_HIGH_TABLES==1 + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_base); + } +#endif } #if CONFIG_AMDMCT == 0 #if HW_MEM_HOLE_SIZEK != 0 @@ -1108,6 +1122,15 @@ static void pci_domain_set_resources(device_t dev) } ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; +#if HAVE_HIGH_TABLES==1 + printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", + i, mmio_basek, basek, limitk); + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif } for(link = 0; link < dev->links; link++) { |