amdfam10: Perform major include ".c" cleanup

Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)

This patch separates the build into separate .o modules
and links them accordingly.

Currently compiles and links all fam10 roms without
breaking other roms.

Both DDR2 and DDR3 have been completed

TESTED on REACTS: passes all boot tests for 2 boards
 ASUS KGPE-D16
 ASUS KFSN4-DRE

Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
 advansus/a785e-i
 asus/m5a88-v
 avalue/eax-785e

A followup patch may be required to fix the above boards.
See FIXME, XXX tags

Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>

18 files changed, 299 insertions, 269 deletions

diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc
index c2b015b955..787f4444ce 100644
--- a/src/northbridge/amd/amdfam10/Makefile.inc
+++ b/src/northbridge/amd/amdfam10/Makefile.inc
@@ -1,18 +1,19 @@
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y)
 
-ramstage-y += northbridge.c
-ramstage-y += misc_control.c
-ramstage-y += link_control.c
-ramstage-y += nb_control.c
-romstage-y += amdfam10_util.c
-ramstage-y += amdfam10_util.c
-
-ramstage-y += ht_config.c
-
+subdirs-y += ../amdht
+subdirs-y += ../amdmct/wrappers
+subdirs-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3
+subdirs-$(CONFIG_DIMM_DDR2) += ../amdmct/mct
+
+# Generic ROMSTAGE stuff
+romstage-y += reset_test.c debug.c setup_resource_map.c raminit_sysinfo_in_ram.c
+romstage-y += raminit_amdmct.c pci.c early_ht.c amdfam10_util.c
+
+# RAMSTAGE
+ramstage-y += northbridge.c misc_control.c link_control.c nb_control.c
+ramstage-y += amdfam10_util.c ht_config.c get_pci1234.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 
-ramstage-y += get_pci1234.c
-
 # Enable this if you want to check the values of the PCI routing registers.
 # Call show_all_routes() anywhere amdfam10.h is included.
 #ramstage-y += util.c
@@ -30,6 +31,4 @@ s3nv-file := $(obj)/coreboot_s3nv.rom
 s3nv-align := $(CONFIG_S3_DATA_SIZE)
 s3nv-type := raw
 
-ramstage-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3/s3utils.c
-
 endif
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 7ba91d7ed1..611291acbd 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -15,8 +15,28 @@
  */
 
 #ifndef AMDFAM10_H
-
 #define AMDFAM10_H
+
+#include <inttypes.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "early_ht.h"
+
+#include "inline_helper.c"
+struct DCTStatStruc;
+struct MCTStatStruc;
+
+#define RES_PCI_IO 0x10
+#define RES_PORT_IO_8 0x22
+#define RES_PORT_IO_32 0x20
+#define RES_MEM_IO 0x40
+
+#define NODE_ID		0x60
+#define HT_INIT_CONTROL	0x6c
+#define HTIC_ColdR_Detect	(1<<4)
+#define HTIC_BIOSR_Detect	(1<<5)
+#define HTIC_INIT_Detect	(1<<6)
+
 /* Definitions of various FAM10 registers */
 /* Function 0 */
 #define HT_TRANSACTION_CONTROL 0x68
@@ -900,14 +920,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 #endif
 #endif
 
-#include "raminit.h"
-
-#include "../amdmct/wrappers/mcti.h"
-#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
-  #include "../amdmct/mct_ddr3/mct_d.h"
-#else
-  #include "../amdmct/mct/mct_d.h"
-#endif
+/* Include wrapper for MCT (works for DDR2 or DDR3) */
+#include <northbridge/amd/amdmct/wrappers/mcti.h>
 
 struct link_pair_t {
 	pci_devfn_t udev;
@@ -965,10 +979,12 @@ struct sys_info {
 	struct DCTStatStruc DCTstatA[NODE_NUMS];
 } __attribute__((packed));
 
+
+/*
 #ifdef __PRE_RAM__
 extern struct sys_info sysinfo_car;
 #endif
-
+*/
 #ifndef __PRE_RAM__
 device_t get_node_pci(u32 nodeid, u32 fn);
 #endif
@@ -983,14 +999,19 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32
 		offset_pci_dev, u32 offset_io_base);
 
 void setup_resource_map_x(const u32 *register_values, u32 max);
+void setup_resource_map(const u32 *register_values, u32 max);
 
 /* reset_test.c */
 u32 cpu_init_detected(u8 nodeid);
 u32 bios_reset_detected(void);
 u32 cold_reset_detected(void);
 u32 other_reset_detected(void);
+u32 warm_reset_detect(u8 nodeid);
+void distinguish_cpu_resets(u8 nodeid);
 u32 get_sblk(void);
 u8 get_sbbusn(u8 sblk);
+void set_bios_reset(void);
+
 #endif
 
 #include "northbridge/amd/amdht/porting.h"
@@ -1005,4 +1026,6 @@ unsigned long northbridge_write_acpi_tables(device_t device,
 void northbridge_acpi_write_vars(device_t device);
 #endif
 
+void set_sysinfo_in_ram(u32 val);
+
 #endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index c9b30f8fb8..e0195c60eb 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -17,8 +17,8 @@
 #include <console/console.h>
 
 #include <arch/cpu.h>
-#include <northbridge/amd/amdmct/wrappers/mcti.h>
-#include <northbridge/amd/amdmct/mct/mct_d.h>
+#include <arch/io.h>
+#include "raminit.h"
 #include <northbridge/amd/amdmct/amddefs.h>
 
 #ifndef __PRE_RAM__
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
index de1b7d1907..6f2910a549 100644
--- a/src/northbridge/amd/amdfam10/bootblock.c
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -1,5 +1,3 @@
-#include <arch/io.h>
-#include <device/pci_def.h>
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static void bootblock_northbridge_init(void) {
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index f9c72668af..ed2b53977d 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -13,26 +13,25 @@
  * GNU General Public License for more details.
  */
 
-/*
- * Generic FAM10 debug code, used by mainboard specific romstage.c
- */
-
-#include "pci.c"
+#include "debug.h"
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
 #include <delay.h>
 
-static inline void print_debug_addr(const char *str, void *val)
+void print_debug_addr(const char *str, void *val)
 {
 #if CONFIG_DEBUG_CAR
 		printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
 #endif
 }
 
-static void print_debug_pci_dev(u32 dev)
+void print_debug_pci_dev(u32 dev)
 {
 	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 }
 
-static inline void print_pci_devices(void)
+void print_pci_devices(void)
 {
 	pci_devfn_t dev;
 	for (dev = PCI_DEV(0, 0, 0);
@@ -57,7 +56,7 @@ static inline void print_pci_devices(void)
 	}
 }
 
-static inline void print_pci_devices_on_bus(u32 busn)
+void print_pci_devices_on_bus(u32 busn)
 {
 	pci_devfn_t dev;
 	for (dev = PCI_DEV(busn, 0, 0);
@@ -82,7 +81,7 @@ static inline void print_pci_devices_on_bus(u32 busn)
 	}
 }
 
-static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
+void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
 {
 	int i;
 	print_debug_pci_dev(dev);
@@ -103,12 +102,12 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
 	printk(BIOS_DEBUG, "\n");
 }
 
-static void dump_pci_device(u32 dev)
+void dump_pci_device(u32 dev)
 {
 	dump_pci_device_range(dev, 0, 4096);
 }
 
-static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
+void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
 					u32 size)
 {
 	int i;
@@ -130,13 +129,13 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
 	printk(BIOS_DEBUG, "\n");
 }
 
-static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
+void dump_pci_device_index_wait(u32 dev, u32 index_reg)
 {
 	dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54);
 	dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz
 }
 
-static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
+void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
 {
 	int i;
 	print_debug_pci_dev(dev);
@@ -156,7 +155,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
 	printk(BIOS_DEBUG, "\n");
 }
 
-static inline void dump_pci_devices(void)
+void dump_pci_devices(void)
 {
 	pci_devfn_t dev;
 	for (dev = PCI_DEV(0, 0, 0);
@@ -181,7 +180,7 @@ static inline void dump_pci_devices(void)
 	}
 }
 
-static inline void dump_pci_devices_on_bus(u32 busn)
+void dump_pci_devices_on_bus(u32 busn)
 {
 	pci_devfn_t dev;
 	for (dev = PCI_DEV(busn, 0, 0);
@@ -207,8 +206,7 @@ static inline void dump_pci_devices_on_bus(u32 busn)
 }
 
 #if CONFIG_DEBUG_SMBUS
-
-static void dump_spd_registers(const struct mem_controller *ctrl)
+void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
 	printk(BIOS_DEBUG, "\n");
@@ -254,7 +252,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
 		}
 	}
 }
-static void dump_smbus_registers(void)
+
+void dump_smbus_registers(void)
 {
 	u32 device;
 	printk(BIOS_DEBUG, "\n");
@@ -279,7 +278,8 @@ static void dump_smbus_registers(void)
 	}
 }
 #endif
-static inline void dump_io_resources(u32 port)
+
+void dump_io_resources(u32 port)
 {
 
 	int i;
@@ -299,7 +299,7 @@ static inline void dump_io_resources(u32 port)
 	}
 }
 
-static inline void dump_mem(u32 start, u32 end)
+void dump_mem(u32 start, u32 end)
 {
 	u32 i;
 	printk(BIOS_DEBUG, "dump_mem:");
@@ -311,3 +311,26 @@ static inline void dump_mem(u32 start, u32 end)
 	}
 	printk(BIOS_DEBUG, "\n");
 }
+
+#if IS_ENABLED(CONFIG_DIMM_DDR2)
+void print_tx(const char *strval, u32 val)
+{
+#if CONFIG_DEBUG_RAM_SETUP
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
+#endif
+}
+
+void print_t(const char *strval)
+{
+#if CONFIG_DEBUG_RAM_SETUP
+	printk(BIOS_DEBUG, "%s", strval);
+#endif
+}
+#endif /* CONFIG_DIMM_DDR2 */
+
+void print_tf(const char *func, const char *strval)
+{
+#if CONFIG_DEBUG_RAM_SETUP
+	printk(BIOS_DEBUG, "%s: %s", func, strval);
+#endif
+}
diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h
new file mode 100644
index 0000000000..df1f3a0b7d
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/debug.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AMDFAM10_DEBUG_H
+#define AMDFAM10_DEBUG_H
+
+#include <inttypes.h>
+#include "pci.h"
+
+void print_debug_addr(const char *str, void *val);
+void print_debug_pci_dev(u32 dev);
+void print_pci_devices(void);
+void print_pci_devices_on_bus(u32 busn);
+void dump_pci_device_range(u32 dev, u32 start_reg, u32 size);
+void dump_pci_device(u32 dev);
+void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
+					u32 size);
+void dump_pci_device_index_wait(u32 dev, u32 index_reg);
+void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length);
+void dump_pci_devices(void);
+void dump_pci_devices_on_bus(u32 busn);
+
+#if CONFIG_DEBUG_SMBUS
+void dump_spd_registers(const struct mem_controller *ctrl);
+void dump_smbus_registers(void);
+#endif
+
+void dump_io_resources(u32 port);
+void dump_mem(u32 start, u32 end);
+
+void print_tx(const char *strval, u32 val);
+void print_t(const char *strval);
+void print_tf(const char *func, const char *strval);
+#endif
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index 36814638a9..c3b02d73a4 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -13,9 +13,14 @@
  * GNU General Public License for more details.
  */
 
+#include "early_ht.h"
+#include <inttypes.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+
 // For SB HT chain only
 // mmconf is not ready yet
-static  void set_bsp_node_CHtExtNodeCfgEn(void)
+void set_bsp_node_CHtExtNodeCfgEn(void)
 {
 #if CONFIG_EXT_RT_TBL_SUPPORT
 	u32 dword;
@@ -34,7 +39,7 @@ static  void set_bsp_node_CHtExtNodeCfgEn(void)
 #endif
 }
 
-static void enumerate_ht_chain(void)
+void enumerate_ht_chain(void)
 {
 #if CONFIG_HT_CHAIN_UNITID_BASE != 0
 /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain),
diff --git a/src/northbridge/amd/amdfam10/early_ht.h b/src/northbridge/amd/amdfam10/early_ht.h
new file mode 100644
index 0000000000..67476fd849
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/early_ht.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef EARLY_HT_H
+#define EARLY_HT_H
+
+void set_bsp_node_CHtExtNodeCfgEn(void);
+void enumerate_ht_chain(void);
+
+#endif
diff --git a/src/northbridge/amd/amdfam10/inline_helper.c b/src/northbridge/amd/amdfam10/inline_helper.c
new file mode 100644
index 0000000000..7f260318f7
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/inline_helper.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+
+static inline uint8_t is_fam15h(void)
+{
+	uint8_t fam15h = 0;
+	uint32_t family;
+
+	family = cpuid_eax(0x80000001);
+	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
+
+	if (family >= 0x6f)
+		/* Family 15h or later */
+		fam15h = 1;
+
+	return fam15h;
+}
diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c
index 468f184db2..a7fbe4cd7b 100644
--- a/src/northbridge/amd/amdfam10/link_control.c
+++ b/src/northbridge/amd/amdfam10/link_control.c
@@ -29,21 +29,6 @@
 
 #include "amdfam10.h"
 
-static inline uint8_t is_fam15h(void)
-{
-	uint8_t fam15h = 0;
-	uint32_t family;
-
-	family = cpuid_eax(0x80000001);
-	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
-	if (family >= 0x6f)
-		/* Family 15h or later */
-		fam15h = 1;
-
-	return fam15h;
-}
-
 static void nb_control_init(struct device *dev)
 {
 	uint8_t enable_c_states;
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 6d757d9af5..c23f04fee3 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -81,21 +81,6 @@ device_t get_node_pci(u32 nodeid, u32 fn)
 #endif
 }
 
-static inline uint8_t is_fam15h(void)
-{
-	uint8_t fam15h = 0;
-	uint32_t family;
-
-	family = cpuid_eax(0x80000001);
-	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
-	if (family >= 0x6f)
-		/* Family 15h or later */
-		fam15h = 1;
-
-	return fam15h;
-}
-
 static void get_fx_devs(void)
 {
 	int i;
diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c
index 03b63b58ca..6c6d717cba 100644
--- a/src/northbridge/amd/amdfam10/pci.c
+++ b/src/northbridge/amd/amdfam10/pci.c
@@ -13,13 +13,11 @@
  * GNU General Public License for more details.
  */
 
+#include "pci.h"
 
-#ifndef AMDFAM10_PCI_C
-#define AMDFAM10_PCI_C
 /* bit [10,8] are dev func, bit[1,0] are dev index */
 
-
-static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index)
+u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index)
 {
 	u32 dword;
 
@@ -29,7 +27,7 @@ static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index)
 }
 
 #ifdef UNUSED_CODE
-static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index,
+void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index,
 		u32 data)
 {
 
@@ -40,7 +38,7 @@ static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index,
 }
 #endif
 
-static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg,
+u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg,
 		u32 index)
 {
 
@@ -56,7 +54,7 @@ static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg,
 }
 
 #ifdef UNUSED_CODE
-static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg,
+void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg,
 		u32 index, u32 data)
 {
 
@@ -71,4 +69,3 @@ static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg,
 
 }
 #endif
-#endif
diff --git a/src/northbridge/amd/amdfam10/pci.h b/src/northbridge/amd/amdfam10/pci.h
new file mode 100644
index 0000000000..8fcdbd8cca
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/pci.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AMDFAM10_PCI_H
+#define AMDFAM10_PCI_H
+
+#include <inttypes.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+
+u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index);
+u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index);
+
+#endif
diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h
index c1ef29ecee..2f9c7bafd6 100644
--- a/src/northbridge/amd/amdfam10/raminit.h
+++ b/src/northbridge/amd/amdfam10/raminit.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,31 +13,31 @@
  * GNU General Public License for more details.
  */
 
-#ifndef RAMINIT_H
-#define RAMINIT_H
+#ifndef AMDFAM10_RAMINIT_H
+#define AMDFAM10_RAMINIT_H
 
-//DDR2 REG and unbuffered : Socket F 1027 and AM3
-/* every channel have 4 DDR2 DIMM for socket F
- *		       2 for socket M2/M3
- *		       1 for socket s1g1
- */
-#define DIMM_SOCKETS 4
-struct mem_controller {
-	u32 node_id;
-	pci_devfn_t f0, f1, f2, f3, f4, f5;
-	/* channel0 is DCT0 --- channelA
-	 * channel1 is DCT1 --- channelB
-	 * can be ganged, a single dual-channel DCT ---> 128 bit
-	 *	 or unganged a two single-channel DCTs ---> 64bit
-	 * When the DCTs are ganged, the writes to DCT1 set of registers
-	 * (F2x1XX) are ignored and reads return all 0's
-	 * The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C,
-	 * and all the associated indexed registers, are still
-	 * independently accessiable
-	 */
-	/* FIXME: I will only support ganged mode for easy support */
-	u8 spd_switch_addr;
-	u8 spd_addr[DIMM_SOCKETS*2];
-};
+#include <device/pci.h>
+#include <northbridge/amd/amdmct/amddefs.h>
+#include <northbridge/amd/amdmct/wrappers/mcti.h>
+
+struct sys_info;
+struct DCTStatStruc;
+struct MCTStatStruc;
+
+int mctRead_SPD(u32 smaddr, u32 reg);
+void mctSMBhub_Init(u32 node);
+void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
+void raminit_amdmct(struct sys_info *sysinfo);
+void amdmct_cbmem_store_info(struct sys_info *sysinfo);
+void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr);
+uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq);
+u8 mctGetProcessorPackageType(void);
+void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val);
+uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg);
+uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index);
+void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data);
+void fam15h_switch_dct(uint32_t dev, uint8_t dct);
+uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg);
+void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val);
 
 #endif
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 86f0788c46..ef54de529a 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
  * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  *
@@ -14,31 +15,26 @@
  * GNU General Public License for more details.
  */
 
+#include <inttypes.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <northbridge/amd/amdfam10/debug.h>
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+
+/* Global allocation of sysinfo_car */
+#include <arch/early_variables.h>
+struct sys_info sysinfo_car CAR_GLOBAL;
 
-#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
-static  void print_tx(const char *strval, u32 val)
-{
-#if CONFIG_DEBUG_RAM_SETUP
-	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
-#endif
-}
+struct mem_controller;
+extern void activate_spd_rom(const struct mem_controller *ctrl);
+extern int spd_read_byte(unsigned device, unsigned address);
 
-static  void print_t(const char *strval)
-{
-#if CONFIG_DEBUG_RAM_SETUP
-	printk(BIOS_DEBUG, "%s", strval);
-#endif
-}
-#endif
-
-static  void print_tf(const char *func, const char *strval)
-{
-#if CONFIG_DEBUG_RAM_SETUP
-	printk(BIOS_DEBUG, "%s: %s", func, strval);
-#endif
-}
-
-static inline void fam15h_switch_dct(uint32_t dev, uint8_t dct)
+void fam15h_switch_dct(uint32_t dev, uint8_t dct)
 {
 	uint32_t dword;
 
@@ -58,7 +54,7 @@ static inline void fam15h_switch_nb_pstate_config_reg(uint32_t dev, uint8_t nb_p
 	Set_NB32(dev, 0x10c, dword);
 }
 
-static inline uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg)
+uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg)
 {
 	if (is_fam15h()) {
 		/* Obtain address of function 0x1 */
@@ -70,7 +66,7 @@ static inline uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg)
 	}
 }
 
-static inline void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val)
+void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val)
 {
 	if (is_fam15h()) {
 		/* Obtain address of function 0x1 */
@@ -82,7 +78,7 @@ static inline void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_
 	}
 }
 
-static inline uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg)
+uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg)
 {
 	if (is_fam15h()) {
 		/* Obtain address of function 0x1 */
@@ -95,7 +91,7 @@ static inline uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t
 	}
 }
 
-static inline void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val)
+void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val)
 {
 	if (is_fam15h()) {
 		/* Obtain address of function 0x1 */
@@ -108,7 +104,7 @@ static inline void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_p
 	}
 }
 
-static inline uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index)
+uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index)
 {
 	if (is_fam15h()) {
 		/* Obtain address of function 0x1 */
@@ -120,7 +116,7 @@ static inline uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32
 	}
 }
 
-static inline void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data)
+void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data)
 {
 	if (is_fam15h()) {
 		/* Obtain address of function 0x1 */
@@ -144,7 +140,7 @@ static uint16_t voltage_index_to_mv(uint8_t index)
 		return 1500;
 }
 
-static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq)
+uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq)
 {
 	/* FIXME
 	 * Mainboards need to be able to specify the maximum number of DIMMs installable per channel
@@ -524,106 +520,6 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
 	return freq;
 }
 
-#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
-#include "amdfam10.h"
-#include "../amdmct/wrappers/mcti.h"
-#include "../amdmct/amddefs.h"
-#include "../amdmct/mct_ddr3/mwlc_d.h"
-#include "../amdmct/mct_ddr3/mct_d.h"
-#include "../amdmct/mct_ddr3/mct_d_gcc.h"
-
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-#include "../amdmct/mct_ddr3/s3utils.c"
-#endif
-
-#include "../amdmct/wrappers/mcti_d.c"
-#include "../amdmct/mct_ddr3/mct_d.c"
-
-#include "../amdmct/mct_ddr3/mctmtr_d.c"
-#include "../amdmct/mct_ddr3/mctcsi_d.c"
-#include "../amdmct/mct_ddr3/mctecc_d.c"
-#include "../amdmct/mct_ddr3/mctdqs_d.c"
-#include "../amdmct/mct_ddr3/mctsrc.c"
-#include "../amdmct/mct_ddr3/mctsdi.c"
-#include "../amdmct/mct_ddr3/mctprod.c"
-#include "../amdmct/mct_ddr3/mctproc.c"
-#include "../amdmct/mct_ddr3/mctprob.c"
-#include "../amdmct/mct_ddr3/mcthwl.c"
-#include "../amdmct/mct_ddr3/mctwl.c"
-#include "../amdmct/mct_ddr3/mport_d.c"
-#include "../amdmct/mct_ddr3/mutilc_d.c"
-#include "../amdmct/mct_ddr3/modtrdim.c"
-#include "../amdmct/mct_ddr3/mhwlc_d.c"
-#include "../amdmct/mct_ddr3/mctrci.c"
-#include "../amdmct/mct_ddr3/mctsrc1p.c"
-#include "../amdmct/mct_ddr3/mcttmrl.c"
-#include "../amdmct/mct_ddr3/mcthdi.c"
-#include "../amdmct/mct_ddr3/mctndi_d.c"
-#include "../amdmct/mct_ddr3/mctchi_d.c"
-#include "../amdmct/mct_ddr3/modtrd.c"
-
-#if CONFIG_CPU_SOCKET_TYPE == 0x10
-//TODO: S1G1?
-#elif CONFIG_CPU_SOCKET_TYPE == 0x11
-//AM3
-#include "../amdmct/mct_ddr3/mctardk5.c"
-#elif CONFIG_CPU_SOCKET_TYPE == 0x12
-//F (1207), Fr2, G (1207)
-#include "../amdmct/mct_ddr3/mctardk6.c"
-#elif CONFIG_CPU_SOCKET_TYPE == 0x13
-//ASB2
-#include "../amdmct/mct_ddr3/mctardk5.c"
-//C32
-#elif CONFIG_CPU_SOCKET_TYPE == 0x14
-#include "../amdmct/mct_ddr3/mctardk5.c"
-//G34
-#elif CONFIG_CPU_SOCKET_TYPE == 0x15
-#include "../amdmct/mct_ddr3/mctardk5.c"
-//FM2
-#elif CONFIG_CPU_SOCKET_TYPE == 0x16
-#include "../amdmct/mct_ddr3/mctardk5.c"
-#endif
-
-#else  /* DDR2 */
-
-#include "amdfam10.h"
-#include "../amdmct/wrappers/mcti.h"
-#include "../amdmct/amddefs.h"
-#include "../amdmct/mct/mct_d.h"
-#include "../amdmct/mct/mct_d_gcc.h"
-
-#include "../amdmct/wrappers/mcti_d.c"
-#include "../amdmct/mct/mct_d.c"
-
-
-#include "../amdmct/mct/mctmtr_d.c"
-#include "../amdmct/mct/mctcsi_d.c"
-#include "../amdmct/mct/mctecc_d.c"
-#include "../amdmct/mct/mctpro_d.c"
-#include "../amdmct/mct/mctdqs_d.c"
-#include "../amdmct/mct/mctsrc.c"
-#include "../amdmct/mct/mctsrc1p.c"
-#include "../amdmct/mct/mcttmrl.c"
-#include "../amdmct/mct/mcthdi.c"
-#include "../amdmct/mct/mctndi_d.c"
-#include "../amdmct/mct/mctchi_d.c"
-
-#if CONFIG_CPU_SOCKET_TYPE == 0x10
-//L1
-#include "../amdmct/mct/mctardk3.c"
-#elif CONFIG_CPU_SOCKET_TYPE == 0x11
-//AM2
-#include "../amdmct/mct/mctardk4.c"
-//#elif SYSTEM_TYPE == MOBILE
-//s1g1
-//#include "../amdmct/mct/mctardk5.c"
-#endif
-
-#endif	/* DDR2 */
-
-#include <arch/early_variables.h>
-struct sys_info sysinfo_car CAR_GLOBAL;
-
 int mctRead_SPD(u32 smaddr, u32 reg)
 {
 	return spd_read_byte(smaddr, reg);
@@ -652,14 +548,14 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
 }
 
 #if IS_ENABLED(CONFIG_SET_FIDVID)
-static u8 mctGetProcessorPackageType(void) {
+u8 mctGetProcessorPackageType(void) {
 	/* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */
 	u32 BrandId = cpuid_ebx(0x80000001);
 	return (u8)((BrandId >> 28) & 0x0F);
 }
 #endif
 
-static void raminit_amdmct(struct sys_info *sysinfo)
+void raminit_amdmct(struct sys_info *sysinfo)
 {
 	struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
 	struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
@@ -671,7 +567,7 @@ static void raminit_amdmct(struct sys_info *sysinfo)
 	printk(BIOS_DEBUG, "raminit_amdmct end:\n");
 }
 
-static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
+void amdmct_cbmem_store_info(struct sys_info *sysinfo)
 {
 	if (!sysinfo)
 		return;
diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
index 0461323666..dce205333f 100644
--- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
+++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
 #include <delay.h>
 
 static void set_htic_bit(u8 i, u32 val, u8 bit)
@@ -45,12 +47,7 @@ static void wait_till_sysinfo_in_ram(void)
 }
 #endif
 
-static void set_sysinfo_in_ram(u32 val)
-{
-	set_htic_bit(0, val, 9);
-}
-
-static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr)
+void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr)
 {
 	int i;
 	int j;
@@ -76,3 +73,8 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
 		}
 	}
 }
+
+void set_sysinfo_in_ram(u32 val)
+{
+	set_htic_bit(0, val, 9);
+}
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 0e64397ff0..22f48b1ab7 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -15,13 +15,8 @@
 
 #include <stdint.h>
 #include <cpu/x86/lapic.h>
-#include "amdfam10.h"
-
-#define NODE_ID		0x60
-#define HT_INIT_CONTROL	0x6c
-#define HTIC_ColdR_Detect	(1<<4)
-#define HTIC_BIOSR_Detect	(1<<5)
-#define HTIC_INIT_Detect	(1<<6)
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
 
 /* mmconf is not ready */
 /* io_ext is not ready */
@@ -60,7 +55,7 @@ u32 other_reset_detected(void)	// other warm reset not started by BIOS
 	return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect);
 }
 
-static void distinguish_cpu_resets(u8 nodeid)
+void distinguish_cpu_resets(u8 nodeid)
 {
 	u32 htic;
 	pci_devfn_t device;
@@ -70,7 +65,7 @@ static void distinguish_cpu_resets(u8 nodeid)
 	pci_io_write_config32(device, HT_INIT_CONTROL, htic);
 }
 
-static u32 warm_reset_detect(u8 nodeid)
+u32 warm_reset_detect(u8 nodeid)
 {
 	u32 htic;
 	pci_devfn_t device;
@@ -79,7 +74,6 @@ static u32 warm_reset_detect(u8 nodeid)
 	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
 }
 
-void set_bios_reset(void);
 void set_bios_reset(void)
 {
 
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 3d67bddba4..23e2ba378c 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -14,10 +14,14 @@
  * GNU General Public License for more details.
  */
 
+#include <inttypes.h>
+#include <console/console.h>
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
 
 #define RES_DEBUG 0
 
-static void setup_resource_map(const u32 *register_values, u32 max)
+void setup_resource_map(const u32 *register_values, u32 max)
 {
 	u32 i;
 
@@ -53,11 +57,6 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p
 	}
 }
 
-#define RES_PCI_IO 0x10
-#define RES_PORT_IO_8 0x22
-#define RES_PORT_IO_32 0x20
-#define RES_MEM_IO 0x40
-
 void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
 {
 	u32 i;