diff options
author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/northbridge/amd/amdfam10/pci.c | |
parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/northbridge/amd/amdfam10/pci.c')
-rw-r--r-- | src/northbridge/amd/amdfam10/pci.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c index 03b63b58ca..6c6d717cba 100644 --- a/src/northbridge/amd/amdfam10/pci.c +++ b/src/northbridge/amd/amdfam10/pci.c @@ -13,13 +13,11 @@ * GNU General Public License for more details. */ +#include "pci.h" -#ifndef AMDFAM10_PCI_C -#define AMDFAM10_PCI_C /* bit [10,8] are dev func, bit[1,0] are dev index */ - -static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) +u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) { u32 dword; @@ -29,7 +27,7 @@ static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) } #ifdef UNUSED_CODE -static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, +void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { @@ -40,7 +38,7 @@ static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, } #endif -static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, +u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index) { @@ -56,7 +54,7 @@ static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, } #ifdef UNUSED_CODE -static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, +void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { @@ -71,4 +69,3 @@ static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, } #endif -#endif |