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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-07 19:06:09 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-22 23:09:01 +0100 |
| commit | 4dc6cabd368f4667c5f96e042daab71d530ac663 (patch) | |
| tree | 6dbb18db796254a707e9a8b5e5696c1c2914ef08 /src/northbridge/amd/amdfam10/nb_control.c | |
| parent | 167c03ad4ac7f9221a8902f5500ea7f891e2ed65 (diff) | |
northbridge/amd/amdfam10: Fix poor performance on Family 15h CPUs
Change-Id: I193749bc767b7c1139de7cd67622a7b03298009b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12031
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/amd/amdfam10/nb_control.c')
| -rw-r--r-- | src/northbridge/amd/amdfam10/nb_control.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c index f95b6f80ae..8e8dd578f2 100644 --- a/src/northbridge/amd/amdfam10/nb_control.c +++ b/src/northbridge/amd/amdfam10/nb_control.c @@ -60,10 +60,10 @@ static void nb_control_init(struct device *dev) pci_write_config32(dev, 0xe0, dword); /* Configure northbridge P-states */ - dword = pci_read_config32(dev, 0xe0); + dword = pci_read_config32(dev, 0x170); dword &= ~(0x7 << 9); /* NbPstateThreshold = compute_unit_count */ dword |= (compute_unit_count & 0x7) << 9; - pci_write_config32(dev, 0xe0, dword); + pci_write_config32(dev, 0x170, dword); printk(BIOS_DEBUG, "done.\n"); } |