diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
| commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
| tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/northbridge/amd/amdfam10/amdfam10_acpi.c | |
| parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10/amdfam10_acpi.c')
| -rw-r--r-- | src/northbridge/amd/amdfam10/amdfam10_acpi.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c index 4651b17157..f902d6ee98 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c +++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c @@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned long current) /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u8 *ln = sysinfox->ln; @@ -190,7 +190,7 @@ void update_ssdt(void *ssdt) u8 *CBST; u8 *CBBX; u8 *CBS2; - u8 *CBB2; + u8 *CONFIG_CBB2; int i; @@ -208,7 +208,7 @@ void update_ssdt(void *ssdt) HCDN = ssdt+0x57a; //+5 will be next HCDN CBBX = ssdt+0x61f; // CBST = ssdt+0x626; - CBB2 = ssdt+0x62d; // + CONFIG_CBB2 = ssdt+0x62d; // CBS2 = ssdt+0x634; for(i=0;i<HC_NUMS;i++) { @@ -245,9 +245,9 @@ void update_ssdt(void *ssdt) int_to_stream(0x20202020, HCDN + i*5); } - *CBBX = (u8)(CBB); + *CBBX = (u8)(CONFIG_CBB); - if(CBB == 0xff) { + if(CONFIG_CBB == 0xff) { *CBST = (u8) (0x0f); } else { if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 @@ -258,12 +258,12 @@ void update_ssdt(void *ssdt) } } - if((CBB == 0xff) && (sysconf.nodes>32)) { + if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) { *CBS2 = 0x0f; - *CBB2 = (u8)(CBB-1); + *CONFIG_CBB2 = (u8)(CONFIG_CBB-1); } else { *CBS2 = 0x00; - *CBB2 = 0x00; + *CONFIG_CBB2 = 0x00; } } |