diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 00:18:43 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 00:18:43 +0000 |
| commit | 0e5d3e16b494aafa3c08a28a0484ee0845d84512 (patch) | |
| tree | 72f4d401f94bfb0f2041f994533faa7ba4207588 /src/northbridge/amd/amdfam10/Kconfig | |
| parent | adb23a51f5f711d10798a0bcddf4764a5dc0ae7c (diff) | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming. A later patch will remove
a part I don't know what's mean to do.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10/Kconfig')
| -rw-r--r-- | src/northbridge/amd/amdfam10/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 8fc2653d02..74e0ff454b 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -112,4 +112,12 @@ if DIMM_DDR3 endif endif +config SVI_HIGH_FREQ + bool + default n + depends on NORTHBRIDGE_AMD_AMDFAM10 + help + Select this for boards with a Voltage Regulator able to operate + at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. + source src/northbridge/amd/amdfam10/root_complex/Kconfig |