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authorAaron Durbin <adurbin@chromium.org>2017-04-16 22:05:36 -0500
committerAaron Durbin <adurbin@chromium.org>2017-04-25 18:14:38 +0200
commite4d7abc0d448c7e805f2b48ed1251708d1f84c67 (patch)
tree4ca1014c9d972063e7b44c8a373072008c6015fa /src/northbridge/amd/agesa
parent4003950881af6fc4761aa0b177a3670d04ee9881 (diff)
lib: provide clearer devicetree semantics
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/amd/agesa')
-rw-r--r--src/northbridge/amd/agesa/family14/dimmSpd.c4
-rw-r--r--src/northbridge/amd/agesa/family15/dimmSpd.c4
-rw-r--r--src/northbridge/amd/agesa/family15rl/dimmSpd.c4
-rw-r--r--src/northbridge/amd/agesa/family15tn/dimmSpd.c4
-rw-r--r--src/northbridge/amd/agesa/family16kb/dimmSpd.c4
5 files changed, 10 insertions, 10 deletions
diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c
index f8c5b02f46..d992414bb5 100644
--- a/src/northbridge/amd/agesa/family14/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family14/dimmSpd.c
@@ -34,11 +34,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
{
UINT8 spdAddress;
- ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
if (dev == NULL)
return AGESA_ERROR;
- ROMSTAGE_CONST struct northbridge_amd_agesa_family14_config *config = dev->chip_info;
+ DEVTREE_CONST struct northbridge_amd_agesa_family14_config *config = dev->chip_info;
if (config == NULL)
return AGESA_ERROR;
diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c
index de75701a8a..3b1220201a 100644
--- a/src/northbridge/amd/agesa/family15/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15/dimmSpd.c
@@ -34,11 +34,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
{
UINT8 spdAddress;
- ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
if (dev == NULL)
return AGESA_ERROR;
- ROMSTAGE_CONST struct northbridge_amd_agesa_family15_config *config = dev->chip_info;
+ DEVTREE_CONST struct northbridge_amd_agesa_family15_config *config = dev->chip_info;
if (config == NULL)
return AGESA_ERROR;
diff --git a/src/northbridge/amd/agesa/family15rl/dimmSpd.c b/src/northbridge/amd/agesa/family15rl/dimmSpd.c
index 2c1de73104..7d0f2a1c9c 100644
--- a/src/northbridge/amd/agesa/family15rl/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15rl/dimmSpd.c
@@ -34,11 +34,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
{
UINT8 spdAddress;
- ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
if (dev == NULL)
return AGESA_ERROR;
- ROMSTAGE_CONST struct northbridge_amd_agesa_family15rl_config *config = dev->chip_info;
+ DEVTREE_CONST struct northbridge_amd_agesa_family15rl_config *config = dev->chip_info;
if (config == NULL)
return AGESA_ERROR;
diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
index de45870601..6273843dbb 100644
--- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
@@ -33,11 +33,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
{
UINT8 spdAddress;
- ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
if (dev == NULL)
return AGESA_ERROR;
- ROMSTAGE_CONST struct northbridge_amd_agesa_family15tn_config *config = dev->chip_info;
+ DEVTREE_CONST struct northbridge_amd_agesa_family15tn_config *config = dev->chip_info;
if (config == NULL)
return AGESA_ERROR;
diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
index 82d67d5038..a2319bc110 100644
--- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
@@ -33,11 +33,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
{
UINT8 spdAddress;
- ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
if (dev == NULL)
return AGESA_ERROR;
- ROMSTAGE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info;
+ DEVTREE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info;
if (config == NULL)
return AGESA_ERROR;