Add AMD Family 10 cpu support to northbridge folder

This change adds the AMD Family 10 cpu support to the northbridge
folder.  The northbridge/amd/agesa Kconfig and Makefile.inc are
changed as well.

Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/98
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

13 files changed, 2195 insertions, 0 deletions

diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index d5fde5766f..463da5d9ce 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -17,6 +17,7 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+source src/northbridge/amd/agesa/family10/Kconfig
 source src/northbridge/amd/agesa/family12/Kconfig
 source src/northbridge/amd/agesa/family14/Kconfig
 
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 96798fc840..1da8f60f17 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -16,5 +16,6 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig
new file mode 100755
index 0000000000..62a6cd4cc5
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/Kconfig
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+config NORTHBRIDGE_AMD_AGESA_FAMILY10
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+	select HAVE_DEBUG_SMBUS
+	select HYPERTRANSPORT_PLUGIN_SUPPORT
+	select MMCONF_SUPPORT
+	select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
+
+if NORTHBRIDGE_AMD_AGESA_FAMILY10
+config HT3_SUPPORT
+	bool
+	default y
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xE0000000
+config MMCONF_BUS_NUMBER
+	int
+	default 256
+config BOOTBLOCK_NORTHBRIDGE_INIT
+  string
+  default "northbridge/amd/agesa/family10/bootblock.c"
+endif #NORTHBRIDGE_AMD_AGESA_FAMILY10
+
+source "src/northbridge/amd/agesa/family10/root_complex/Kconfig"
diff --git a/src/northbridge/amd/agesa/family10/Makefile.inc b/src/northbridge/amd/agesa/family10/Makefile.inc
new file mode 100755
index 0000000000..8f0fe0d773
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h
new file mode 100755
index 0000000000..e6f9d81b83
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/amdfam10.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef AMDFAM10_H
+#define AMDFAM10_H
+
+#include <cpu/x86/msr.h>
+
+#define HWCR_MSR                        0xC0010015
+#define NB_CFG_MSR                      0xC001001f
+#define LS_CFG_MSR                      0xC0011020
+#define IC_CFG_MSR                      0xC0011021
+#define DC_CFG_MSR                      0xC0011022
+#define BU_CFG_MSR                      0xC0011023
+#define BU_CFG2_MSR                     0xC001102A
+
+#define CPU_ID_FEATURES_MSR		0xC0011004
+#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
+
+/* Definitions of various FAM10 registers */
+/* Function 0 */
+#define HT_TRANSACTION_CONTROL 0x68
+#define  HTTC_DIS_RD_B_P		(1 << 0)
+#define  HTTC_DIS_RD_DW_P		(1 << 1)
+#define  HTTC_DIS_WR_B_P		(1 << 2)
+#define  HTTC_DIS_WR_DW_P		(1 << 3)
+#define  HTTC_DIS_MTS			(1 << 4)
+#define  HTTC_CPU1_EN			(1 << 5)
+#define  HTTC_CPU_REQ_PASS_PW		(1 << 6)
+#define  HTTC_CPU_RD_RSP_PASS_PW	(1 << 7)
+#define  HTTC_DIS_P_MEM_C		(1 << 8)
+#define  HTTC_DIS_RMT_MEM_C		(1 << 9)
+#define  HTTC_DIS_FILL_P		(1 << 10)
+#define  HTTC_RSP_PASS_PW		(1 << 11)
+#define  HTTC_BUF_REL_PRI_SHIFT	13
+#define  HTTC_BUF_REL_PRI_MASK		3
+#define   HTTC_BUF_REL_PRI_64		0
+#define   HTTC_BUF_REL_PRI_16		1
+#define   HTTC_BUF_REL_PRI_8		2
+#define   HTTC_BUF_REL_PRI_2		3
+#define  HTTC_LIMIT_CLDT_CFG		(1 << 15)
+#define  HTTC_LINT_EN			(1 << 16)
+#define  HTTC_APIC_EXT_BRD_CST		(1 << 17)
+#define  HTTC_APIC_EXT_ID		(1 << 18)
+#define  HTTC_APIC_EXT_SPUR		(1 << 19)
+#define  HTTC_SEQ_ID_SRC_NODE_EN	(1 << 20)
+#define  HTTC_DS_NP_REQ_LIMIT_SHIFT	21
+#define  HTTC_DS_NP_REQ_LIMIT_MASK	3
+#define   HTTC_DS_NP_REQ_LIMIT_NONE	0
+#define   HTTC_DS_NP_REQ_LIMIT_1	1
+#define   HTTC_DS_NP_REQ_LIMIT_4	2
+#define   HTTC_DS_NP_REQ_LIMIT_8	3
+
+/* Function 1 */
+
+/* Function 2 */
+
+/* Function 3 */
+
+
+/* Function 5 for FBDIMM */
+#define LinkConnected		(1 << 0)
+#define InitComplete		(1 << 1)
+#define NonCoherent		(1 << 2)
+#define ConnectionPending	(1 << 4)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 8
+	#if CONFIG_MAX_PHYSICAL_CPUS > 32
+		#define NODE_NUMS 64
+	#else
+		#define NODE_NUMS 32
+	#endif
+#else
+	#define NODE_NUMS 8
+#endif
+
+#ifdef __PRE_RAM__
+#if NODE_NUMS==64
+	 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+	 #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+#endif
+
+#endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
new file mode 100755
index 0000000000..f6ae8be8b9
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/bootblock.c
@@ -0,0 +1,29 @@
+/*
+ *****************************************************************************
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * ***************************************************************************
+ *
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+
+static void bootblock_northbridge_init(void) {
+}
diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h
new file mode 100755
index 0000000000..c0ac56e5a9
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_amd_agesa_family10_config
+{
+};
+
+extern struct chip_operations northbridge_amd_agesa_family10_ops;
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
new file mode 100755
index 0000000000..b3e4c63d00
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -0,0 +1,1518 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+
+#if CONFIG_LOGICAL_CPUS==1
+#include <pc80/mc146818rtc.h>
+#endif
+
+#include <cpu/amd/amdfam10_sysconf.h>
+#include <Porting.h>
+#include <AGESA.h>
+#include <Options.h>
+#include "root_complex/chip.h"
+#include "northbridge.h"
+#include "amdfam10.h"
+#include "chip.h"
+
+extern uint32_t agesawrapper_amdinitmid(void);
+
+typedef struct amdfam10_sysconf_t sys_info_conf_t;
+typedef struct dram_base_mask {
+        u32 base; //[47:27] at [28:8]
+        u32 mask; //[47:27] at [28:8] and enable at bit 0
+} dram_base_mask_t;
+
+
+struct amdfam10_sysconf_t sysconf;
+static device_t __f0_dev[NODE_NUMS];
+static device_t __f1_dev[NODE_NUMS];
+static device_t __f2_dev[NODE_NUMS];
+static device_t __f4_dev[NODE_NUMS];
+static unsigned fx_devs = 0;
+
+#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1
+#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
+#endif
+
+static dram_base_mask_t get_dram_base_mask(u32 nodeid)
+{
+	device_t dev;
+	dram_base_mask_t d;
+	dev = __f1_dev[0];
+
+#if CONFIG_EXT_CONF_SUPPORT == 1
+	/* I will use ext space only for simple */
+	pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
+	d.mask = pci_read_config32(dev, 0x114);  // enable is bit 0
+	pci_write_config32(dev, 0x110, nodeid | (0<<28));
+	d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8];
+#else
+	u32 temp;
+	temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
+	d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out  DramMask [26:24] too
+	temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+	d.mask |= temp<<21;
+
+	temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
+	d.mask |= (temp & 1); // enable bit
+
+	d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
+	temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+	d.base |= temp<<21;
+#endif
+	return d;
+}
+
+#if CONFIG_EXT_CONF_SUPPORT
+static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
+						u32 busn_min, u32 busn_max,
+						u32 type)
+{
+	device_t dev;
+	u32 i;
+	u32 tempreg;
+	u32 index_min, index_max;
+	u32 dest_min, dest_max;
+	index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
+	index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
+
+	// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
+	dev = __f1_dev[nodeid];
+	if (index_min== index_max) {
+		pci_write_config32(dev, 0x110, index_min | (type<<28));
+		tempreg = pci_read_config32(dev, 0x114);
+		for (i=dest_min; i<=dest_max; i++) {
+			tempreg &= ~(0xff<<(i*8));
+			tempreg |= (cfg_map_dest<<(i*8));
+		}
+		pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
+		pci_write_config32(dev, 0x114, tempreg);
+	} else if (index_min<index_max) {
+		pci_write_config32(dev, 0x110, index_min | (type<<28));
+		tempreg = pci_read_config32(dev, 0x114);
+		for (i=dest_min; i<=3; i++) {
+			tempreg &= ~(0xff<<(i*8));
+			tempreg |= (cfg_map_dest<<(i*8));
+		}
+		pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
+		pci_write_config32(dev, 0x114, tempreg);
+
+		pci_write_config32(dev, 0x110, index_max | (type<<28));
+		tempreg = pci_read_config32(dev, 0x114);
+		for (i=0; i<=dest_max; i++) {
+			tempreg &= ~(0xff<<(i*8));
+			tempreg |= (cfg_map_dest<<(i*8));
+		}
+		pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
+		pci_write_config32(dev, 0x114, tempreg);
+		if ((index_max-index_min)>1) {
+			tempreg = 0;
+			for (i=0; i<=3; i++) {
+				tempreg &= ~(0xff<<(i*8));
+				tempreg |= (cfg_map_dest<<(i*8));
+			}
+			for (i=index_min+1; i<index_max;i++) {
+				pci_write_config32(dev, 0x110, i | (type<<28));
+				pci_write_config32(dev, 0x114, tempreg);
+			}
+		}
+	}
+}
+#endif
+
+#if CONFIG_PCI_BUS_SEGN_BITS
+static u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
+			sys_info_conf_t *sysinfo)
+{
+	//check segbusn here, We need every node have the same segn
+	if ((segbusn & 0xff)>(0xe0-1)) {// use next segn
+		u32 segn = (segbusn >> 8) & 0x0f;
+		segn++;
+		segbusn = segn<<8;
+	}
+	if (segbusn>>8) {
+		u32 val;
+		val = pci_read_config32(dev, 0x160);
+		val &= ~(0xf<<25);
+		val |= (segbusn & 0xf00)<<(25-8);
+		pci_write_config32(dev, 0x160, val);
+	}
+
+	return segbusn;
+}
+#endif
+
+static u32 get_io_addr_index(u32 nodeid, u32 linkn)
+{
+	u32 index;
+
+	for (index=0; index<256; index++) {
+		if ((sysconf.conf_io_addrx[index+4] == 0)) {
+			sysconf.conf_io_addr[index+4] =  (nodeid & 0x3f)  ;
+			sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
+			return index;
+		 }
+	 }
+
+	 return	 0;
+
+}
+
+static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
+{
+	u32 index;
+
+	for (index=0; index<64; index++) {
+		if ((sysconf.conf_mmio_addrx[index+8] == 0)) {
+			sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
+			sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
+			return index;
+		}
+	}
+
+	return	 0;
+}
+
+static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
+				u32 io_min, u32 io_max)
+{
+	u32 val;
+#if CONFIG_EXT_CONF_SUPPORT
+	if (reg!=0x110) {
+#endif
+		/* io range allocation */
+		index = (reg-0xc0)>>3;
+#if CONFIG_EXT_CONF_SUPPORT
+	} else {
+		index+=4;
+	}
+#endif
+
+	val = (nodeid & 0x3f); // 6 bits used
+	sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
+	val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+	sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit
+
+	if (sysconf.io_addr_num<(index+1))
+		sysconf.io_addr_num = index+1;
+}
+
+static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
+					u32 mmio_min, u32 mmio_max)
+{
+	u32 val;
+#if CONFIG_EXT_CONF_SUPPORT
+	if (reg!=0x110) {
+#endif
+		/* io range allocation */
+		index = (reg-0x80)>>3;
+#if CONFIG_EXT_CONF_SUPPORT
+	} else {
+		index += 8;
+	}
+#endif
+
+	val = (nodeid & 0x3f) ; // 6 bits used
+	sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
+	val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+	sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit
+
+	if (sysconf.mmio_addr_num<(index+1))
+		sysconf.mmio_addr_num = index+1;
+}
+
+static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+				u32 io_min, u32 io_max)
+{
+
+	u32 i;
+	u32 tempreg;
+#if CONFIG_EXT_CONF_SUPPORT
+	if (reg!=0x110) {
+#endif
+		/* io range allocation */
+		tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
+		for (i=0; i<sysconf.nodes; i++)
+			pci_write_config32(__f1_dev[i], reg+4, tempreg);
+
+		tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
+#if 0
+		// FIXME: can we use VGA reg instead?
+		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
+				__func__, dev_path(dev), link);
+			tempreg |= PCI_IO_BASE_VGA_EN;
+		}
+		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+			tempreg |= PCI_IO_BASE_NO_ISA;
+		}
+#endif
+		for (i=0; i<sysconf.nodes; i++)
+			pci_write_config32(__f1_dev[i], reg, tempreg);
+#if CONFIG_EXT_CONF_SUPPORT
+		return;
+	}
+
+	u32 cfg_map_dest;
+	u32 j;
+	// if ht_c_index > 3, We should use extend space
+	if (io_min>io_max) return;
+	// for nodeid at first
+	cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
+
+	set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
+
+	// all other nodes
+	cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
+	for (j = 0; j< sysconf.nodes; j++) {
+		if (j== nodeid) continue;
+		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+	}
+#endif
+}
+
+static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
+{
+
+	u32 i;
+	u32 tempreg;
+#if CONFIG_EXT_CONF_SUPPORT
+	if (reg!=0x110) {
+#endif
+		/* io range allocation */
+		tempreg = (nodeid&0xf) | (linkn<<4) |	 (mmio_max&0xffffff00); //limit
+		for (i=0; i<nodes; i++)
+			pci_write_config32(__f1_dev[i], reg+4, tempreg);
+		tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
+		for (i=0; i<sysconf.nodes; i++)
+			pci_write_config32(__f1_dev[i], reg, tempreg);
+#if CONFIG_EXT_CONF_SUPPORT
+		return;
+	}
+
+	device_t dev;
+	u32 j;
+	// if ht_c_index > 3, We should use extend space
+	// for nodeid at first
+	u32 enable;
+
+	if (mmio_min>mmio_max) {
+		return;
+	}
+
+	enable = 1;
+	dev = __f1_dev[nodeid];
+	tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
+	pci_write_config32(dev, 0x110, index | (2<<28));
+	pci_write_config32(dev, 0x114, tempreg);
+
+	tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
+	pci_write_config32(dev, 0x110, index | (3<<28));
+	pci_write_config32(dev, 0x114, tempreg);
+
+	// all other nodes
+	tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0);
+	for (j = 0; j< sysconf.nodes; j++) {
+		if (j== nodeid) continue;
+		dev = __f1_dev[j];
+		pci_write_config32(dev, 0x110, index | (2<<28));
+		pci_write_config32(dev, 0x114, tempreg);
+	}
+
+	tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
+	for (j = 0; j< sysconf.nodes; j++) {
+		if(j==nodeid) continue;
+		dev = __f1_dev[j];
+		pci_write_config32(dev, 0x110, index | (3<<28));
+		pci_write_config32(dev, 0x114, tempreg);
+	 }
+#endif
+}
+
+static device_t get_node_pci(u32 nodeid, u32 fn)
+{
+#if NODE_NUMS == 64
+	if (nodeid < 32) {
+		return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	} else {
+		return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
+	}
+
+#else
+	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+#endif
+}
+
+static unsigned int read_nb_cfg_54(void)
+{
+        msr_t msr;
+        msr = rdmsr(NB_CFG_MSR);
+        return (( msr.hi >> (54-32)) & 1);
+}
+
+static void get_fx_devs(void)
+{
+	int i;
+	for (i = 0; i < NODE_NUMS; i++) {
+		__f0_dev[i] = get_node_pci(i, 0);
+		__f1_dev[i] = get_node_pci(i, 1);
+		__f2_dev[i] = get_node_pci(i, 2);
+		__f4_dev[i] = get_node_pci(i, 4);
+		if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+			fx_devs = i+1;
+	}
+	if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+		die("Cannot find 0:0x18.[0|1]\n");
+	}
+}
+
+static u32 f1_read_config32(unsigned reg)
+{
+	if (fx_devs == 0)
+		get_fx_devs();
+	return pci_read_config32(__f1_dev[0], reg);
+}
+
+static void f1_write_config32(unsigned reg, u32 value)
+{
+	int i;
+	if (fx_devs == 0)
+		get_fx_devs();
+	for(i = 0; i < fx_devs; i++) {
+		device_t dev;
+		dev = __f1_dev[i];
+		if (dev && dev->enabled) {
+			pci_write_config32(dev, reg, value);
+		}
+	}
+}
+
+static u32 amdfam10_nodeid(device_t dev)
+{
+#if NODE_NUMS == 64
+	unsigned busn;
+	busn = dev->bus->secondary;
+	if (busn != CONFIG_CBB) {
+		return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
+	} else {
+		return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+	}
+
+#else
+	return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+#endif
+}
+
+static void set_vga_enable_reg(u32 nodeid, u32 linkn)
+{
+	u32 val;
+
+	val =  1 | (nodeid<<4) | (linkn<<12);
+	/* it will routing (1)mmio  0xa0000:0xbffff (2) io 0x3b0:0x3bb,
+	 0x3c0:0x3df */
+	f1_write_config32(0xf4, val);
+
+}
+
+static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+			unsigned goal_link)
+{
+	struct resource *res;
+	unsigned nodeid, link = 0;
+	int result;
+	res = 0;
+	for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
+		device_t dev;
+		dev = __f0_dev[nodeid];
+		if (!dev)
+			continue;
+		for (link = 0; !res && (link < 8); link++) {
+			res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
+		}
+	}
+	result = 2;
+	if (res) {
+		result = 0;
+		if (	(goal_link == (link - 1)) &&
+			(goal_nodeid == (nodeid - 1)) &&
+			(res->flags <= 1)) {
+			result = 1;
+		}
+	}
+	return result;
+}
+
+static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+{
+	struct resource *resource;
+	u32 free_reg, reg;
+	resource = 0;
+	free_reg = 0;
+
+	for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+		int result;
+		result = reg_useable(reg, dev, nodeid, link);
+		if (result == 1) {
+			/* I have been allocated this one */
+			break;
+		}
+		else if (result > 1) {
+			/* I have a free register pair */
+			free_reg = reg;
+		}
+	}
+	if (reg > 0xd8) {
+		reg = free_reg; // if no free, the free_reg still be 0
+	}
+
+	//Ext conf space
+	if(!reg) {
+		//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
+		u32 index = get_io_addr_index(nodeid, link);
+		reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
+	}
+
+	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+
+	return resource;
+}
+
+static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link)
+{
+	struct resource *resource;
+	u32 free_reg, reg;
+	resource = 0;
+	free_reg = 0;
+
+	for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
+		int result;
+		result = reg_useable(reg, dev, nodeid, link);
+		if (result == 1) {
+			/* I have been allocated this one */
+			break;
+		}
+		else if (result > 1) {
+			/* I have a free register pair */
+			free_reg = reg;
+		}
+	}
+	if (reg > 0xb8) {
+		reg = free_reg;
+	}
+
+	//Ext conf space
+	if (!reg) {
+		//because of Extend conf space, we will never run out of reg,
+		// but we need one index to differ them. so same node and
+		// same link can have multi range
+		u32 index = get_mmio_addr_index(nodeid, link);
+		reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
+
+	}
+	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+	return resource;
+}
+
+static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
+{
+	struct resource *resource;
+
+	/* Initialize the io space constraints on the current bus */
+	resource = amdfam10_find_iopair(dev, nodeid, link);
+	if (resource) {
+		u32 align;
+#if CONFIG_EXT_CONF_SUPPORT == 1
+		if((resource->index & 0x1fff) == 0x1110) { // ext
+			align = 8;
+		}
+		else
+#endif
+			align = log2(HT_IO_HOST_ALIGN);
+		resource->base	= 0;
+		resource->size	= 0;
+		resource->align = align;
+		resource->gran	= align;
+		resource->limit = 0xffffUL;
+		resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
+	}
+
+	/* Initialize the prefetchable memory constraints on the current bus */
+	resource = amdfam10_find_mempair(dev, nodeid, link);
+	if (resource) {
+		resource->base = 0;
+		resource->size = 0;
+		resource->align = log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
+		resource->limit = 0xffffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+		resource->flags |= IORESOURCE_BRIDGE;
+
+#if CONFIG_EXT_CONF_SUPPORT == 1
+		if ((resource->index & 0x1fff) == 0x1110) { // ext
+			normalize_resource(resource);
+		}
+#endif
+
+	}
+
+	/* Initialize the memory constraints on the current bus */
+	resource = amdfam10_find_mempair(dev, nodeid, link);
+	if (resource) {
+		resource->base = 0;
+		resource->size = 0;
+		resource->align = log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
+		resource->limit = 0xffffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
+#if CONFIG_EXT_CONF_SUPPORT == 1
+		if ((resource->index & 0x1fff) == 0x1110) { // ext
+			normalize_resource(resource);
+		}
+#endif
+	}
+}
+
+static void amdfam10_read_resources(device_t dev)
+{
+	u32 nodeid;
+	struct bus *link;
+	nodeid = amdfam10_nodeid(dev);
+	for (link = dev->link_list; link; link = link->next) {
+		if (link->children) {
+			amdfam10_link_read_bases(dev, nodeid, link->link_num);
+		}
+	}
+}
+
+static void amdfam10_set_resource(device_t dev, struct resource *resource,
+				u32 nodeid)
+{
+	resource_t rbase, rend;
+	unsigned reg, link_num;
+	char buf[50];
+
+	/* Make certain the resource has actually been set */
+	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		return;
+	}
+
+	/* If I have already stored this resource don't worry about it */
+	if (resource->flags & IORESOURCE_STORED) {
+		return;
+	}
+
+	/* Only handle PCI memory and IO resources */
+	if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+		return;
+
+	/* Ensure I am actually looking at a resource of function 1 */
+	if ((resource->index & 0xffff) < 0x1000) {
+		return;
+	}
+	/* Get the base address */
+	rbase = resource->base;
+
+	/* Get the limit (rounded up) */
+	rend  = resource_end(resource);
+
+	/* Get the register and link */
+	reg  = resource->index & 0xfff; // 4k
+	link_num = IOINDEX_LINK(resource->index);
+
+	if (resource->flags & IORESOURCE_IO) {
+
+		set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
+		store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8);
+	}
+	else if (resource->flags & IORESOURCE_MEM) {
+		set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
+		store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);
+	}
+	resource->flags |= IORESOURCE_STORED;
+	sprintf(buf, " <node %x link %x>",
+			nodeid, link_num);
+	report_resource_stored(dev, resource, buf);
+}
+
+/**
+ * I tried to reuse the resource allocation code in amdfam10_set_resource()
+ * but it is too difficult to deal with the resource allocation magic.
+ */
+
+static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
+{
+	struct bus *link;
+
+	/* find out which link the VGA card is connected,
+	 * we only deal with the 'first' vga card */
+	for (link = dev->link_list; link; link = link->next) {
+		if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+			extern device_t vga_pri; // the primary vga device, defined in device.c
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
+					link->secondary,link->subordinate);
+			/* We need to make sure the vga_pri is under the link */
+			if((vga_pri->bus->secondary >= link->secondary ) &&
+					(vga_pri->bus->secondary <= link->subordinate )
+			  )
+#endif
+				break;
+		}
+	}
+
+	/* no VGA card installed */
+	if (link == NULL)
+		return;
+
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
+	set_vga_enable_reg(nodeid, link->link_num);
+}
+
+static void amdfam10_set_resources(device_t dev)
+{
+	unsigned nodeid;
+	struct bus *bus;
+	struct resource *res;
+
+	/* Find the nodeid */
+	nodeid = amdfam10_nodeid(dev);
+
+	amdfam10_create_vga_resource(dev, nodeid);
+
+	/* Set each resource we have found */
+	for (res = dev->resource_list; res; res = res->next) {
+		amdfam10_set_resource(dev, res, nodeid);
+	}
+
+	for (bus = dev->link_list; bus; bus = bus->next) {
+		if (bus->children) {
+			assign_resources(bus);
+		}
+	}
+}
+
+static void mcf0_control_init(struct device *dev)
+{
+}
+
+static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
+{
+	unsigned nodeid;
+	struct bus *link;
+	unsigned sblink = sysconf.sblk;
+	device_t io_hub = NULL;
+	u32 next_unitid = 0xff;
+
+	nodeid = amdfam10_nodeid(dev);
+	if (nodeid == 0) {
+		for (link = dev->link_list; link; link = link->next) {
+			if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */
+				io_hub = link->children;
+				if (!io_hub || !io_hub->enabled) {
+					die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");
+				}
+				/* Now that nothing is overlapping it is safe to scan the children. */
+				max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0);
+			}
+		}
+	}
+
+	return max;
+}
+
+static struct device_operations northbridge_operations = {
+	.read_resources	  = amdfam10_read_resources,
+	.set_resources	  = amdfam10_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = mcf0_control_init,
+	.scan_bus	  = amdfam10_scan_chains,
+	.enable		  = 0,
+	.ops_pci	  = 0,
+};
+
+static const struct pci_driver mcf0_driver __pci_driver = {
+	.ops	= &northbridge_operations,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x1200,
+};
+
+struct chip_operations northbridge_amd_agesa_family10_ops = {
+	CHIP_NAME("AMD FAM10 Northbridge")
+	.enable_dev = 0,
+};
+
+
+static void amdfam10_domain_read_resources(device_t dev)
+{
+	unsigned reg;
+
+	/* Find the already assigned resource pairs */
+	get_fx_devs();
+	for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
+		u32 base, limit;
+		base  = f1_read_config32(reg);
+		limit = f1_read_config32(reg + 0x04);
+		/* Is this register allocated? */
+		if ((base & 3) != 0) {
+			unsigned nodeid, reg_link;
+			device_t reg_dev;
+			if (reg<0xc0) { // mmio
+				nodeid = (limit & 0xf) + (base&0x30);
+			} else { // io
+				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
+			}
+			reg_link = (limit >> 4) & 7;
+			reg_dev = __f0_dev[nodeid];
+			if (reg_dev) {
+				/* Reserve the resource  */
+				struct resource *res;
+				res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
+				if (res) {
+					res->flags = 1;
+				}
+			}
+		}
+	}
+	/* FIXME: do we need to check extend conf space?
+	   I don't believe that much preset value */
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 0
+	pci_domain_read_resources(dev);
+#else
+	struct bus *link;
+	struct resource *resource;
+	for (link=dev->link_list; link; link = link->next) {
+		/* Initialize the system wide io space constraints */
+		resource = new_resource(dev, 0|(link->link_num<<2));
+		resource->base	= 0x400;
+		resource->limit = 0xffffUL;
+		resource->flags = IORESOURCE_IO;
+
+		/* Initialize the system wide prefetchable memory resources constraints */
+		resource = new_resource(dev, 1|(link->link_num<<2));
+		resource->limit = 0xfcffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+
+		/* Initialize the system wide memory resources constraints */
+		resource = new_resource(dev, 2|(link->link_num<<2));
+		resource->limit = 0xfcffffffffULL;
+		resource->flags = IORESOURCE_MEM;
+	}
+#endif
+}
+
+static void amdfam10_domain_enable_resources(device_t dev)
+{
+	u32 val;
+	/* Must be called after PCI enumeration and resource allocation */
+	printk(BIOS_DEBUG, "\nFam10 - domain_enable_resources: AmdInitMid.\n");
+	val = agesawrapper_amdinitmid();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
+}
+
+
+static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
+{
+	struct resource *min;
+	min = 0;
+	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+	if (min && tolm > min->base) {
+		tolm = min->base;
+	}
+	return tolm;
+}
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+struct hw_mem_hole_info {
+	unsigned hole_startk;
+	int node_id;
+};
+
+static struct hw_mem_hole_info get_hw_mem_hole_info(void)
+{
+	struct hw_mem_hole_info mem_hole;
+	int i;
+
+	mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+	mem_hole.node_id = -1;
+
+	for (i = 0; i < sysconf.nodes; i++) {
+		dram_base_mask_t d;
+		u32 hole;
+		d = get_dram_base_mask(i);
+		if (!(d.mask & 1)) continue; // no memory on this node
+
+		hole = pci_read_config32(__f1_dev[i], 0xf0);
+		if (hole & 1) { // we find the hole
+			mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+			mem_hole.node_id = i; // record the node No with hole
+			break; // only one hole
+		}
+	}
+
+	//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
+	if (mem_hole.node_id == -1) {
+		resource_t limitk_pri = 0;
+		for (i=0; i<sysconf.nodes; i++) {
+			dram_base_mask_t d;
+			resource_t base_k, limit_k;
+			d = get_dram_base_mask(i);
+			if (!(d.base & 1)) continue;
+
+			base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
+			if (base_k > 4 *1024 * 1024) break; // don't need to go to check
+			if (limitk_pri != base_k) { // we find the hole
+				mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
+				mem_hole.node_id = i;
+				break; //only one hole
+			}
+
+			limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
+			limitk_pri = limit_k;
+		}
+	}
+	return mem_hole;
+}
+#endif
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64	// maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
+#if CONFIG_GFXUMA == 1
+extern uint64_t uma_memory_base, uma_memory_size;
+
+static void add_uma_resource(struct device *dev, int index)
+{
+	struct resource *resource;
+
+	printk(BIOS_DEBUG, "Adding UMA memory area\n");
+	resource = new_resource(dev, index);
+	resource->base = (resource_t) uma_memory_base;
+	resource->size = (resource_t) uma_memory_size;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+#endif
+
+static void amdfam10_domain_set_resources(device_t dev)
+{
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+	struct resource *io, *mem1, *mem2;
+	struct resource *res;
+#endif
+	unsigned long mmio_basek;
+	u32 pci_tolm;
+	int i, idx;
+	struct bus *link;
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+	struct hw_mem_hole_info mem_hole;
+	u32 reset_memhole = 1;
+#endif
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+
+	for (link = dev->link_list; link; link = link->next) {
+		/* Now reallocate the pci resources memory with the
+		 * highest addresses I can manage.
+		 */
+		mem1 = find_resource(dev, 1|(link->link_num<<2));
+		mem2 = find_resource(dev, 2|(link->link_num<<2));
+
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+			mem1->base, mem1->limit, mem1->size, mem1->align);
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+			mem2->base, mem2->limit, mem2->size, mem2->align);
+
+		/* See if both resources have roughly the same limits */
+		if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
+			((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
+		{
+			/* If so place the one with the most stringent alignment first
+			 */
+			if (mem2->align > mem1->align) {
+				struct resource *tmp;
+				tmp = mem1;
+				mem1 = mem2;
+				mem2 = tmp;
+			}
+			/* Now place the memory as high up as it will go */
+			mem2->base = resource_max(mem2);
+			mem1->limit = mem2->base - 1;
+			mem1->base = resource_max(mem1);
+		}
+		else {
+			/* Place the resources as high up as they will go */
+			mem2->base = resource_max(mem2);
+			mem1->base = resource_max(mem1);
+		}
+
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+			mem1->base, mem1->limit, mem1->size, mem1->align);
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+			mem2->base, mem2->limit, mem2->size, mem2->align);
+	}
+
+	for (res = &dev->resource_list; res; res = res->next)
+	{
+		res->flags |= IORESOURCE_ASSIGNED;
+		res->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, res, "");
+	}
+#endif
+
+	pci_tolm = 0xffffffffUL;
+	for (link = dev->link_list; link; link = link->next) {
+		pci_tolm = my_find_pci_tolm(link, pci_tolm);
+	}
+
+	// FIXME handle interleaved nodes. If you fix this here, please fix
+	// amdk8, too.
+	mmio_basek = pci_tolm >> 10;
+	/* Round mmio_basek to something the processor can support */
+	mmio_basek &= ~((1 << 6) -1);
+
+	// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
+	// MMIO hole. If you fix this here, please fix amdk8, too.
+	/* Round the mmio hole to 64M */
+	mmio_basek &= ~((64*1024) - 1);
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+/* if the hw mem hole is already set in raminit stage, here we will compare
+ * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
+ * use hole_basek as mmio_basek and we don't need to reset hole.
+ * otherwise We reset the hole to the mmio_basek
+ */
+
+	mem_hole = get_hw_mem_hole_info();
+
+	// Use hole_basek as mmio_basek, and we don't need to reset hole anymore
+	if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) {
+		mmio_basek = mem_hole.hole_startk;
+		reset_memhole = 0;
+	}
+
+#endif
+
+	idx = 0x10;
+	for (i = 0; i < sysconf.nodes; i++) {
+		dram_base_mask_t d;
+		resource_t basek, limitk, sizek; // 4 1T
+		d = get_dram_base_mask(i);
+
+		if (!(d.mask & 1)) continue;
+		basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
+		limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ;
+		sizek = limitk - basek;
+
+		/* see if we need a hole from 0xa0000 to 0xbffff */
+		if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
+			ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
+			idx += 0x10;
+			basek = (8*64)+(16*16);
+			sizek = limitk - ((8*64)+(16*16));
+
+		}
+
+		//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
+
+		/* split the region to accomodate pci memory space */
+		if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+			if (basek <= mmio_basek) {
+				unsigned pre_sizek;
+				pre_sizek = mmio_basek - basek;
+				if (pre_sizek>0) {
+					ram_resource(dev, (idx | i), basek, pre_sizek);
+					idx += 0x10;
+					sizek -= pre_sizek;
+#if CONFIG_WRITE_HIGH_TABLES==1
+					if (high_tables_base==0) {
+					/* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+						high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+#else
+						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
+#endif
+						high_tables_size = HIGH_TABLES_SIZE * 1024;
+						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
+							     high_tables_base);
+					}
+#endif
+				}
+				basek = mmio_basek;
+			}
+			if ((basek + sizek) <= 4*1024*1024) {
+				sizek = 0;
+			}
+			else {
+				basek = 4*1024*1024;
+				sizek -= (4*1024*1024 - mmio_basek);
+			}
+		}
+
+#if CONFIG_GFXUMA == 1
+		/* Deduct uma memory before reporting because
+		 * this is what the mtrr code expects */
+		sizek -= uma_memory_size / 1024;
+#endif
+		ram_resource(dev, (idx | i), basek, sizek);
+		idx += 0x10;
+#if CONFIG_WRITE_HIGH_TABLES==1
+		printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
+			     i, mmio_basek, basek, limitk);
+		if (high_tables_base==0) {
+		/* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+			high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+#else
+			high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+#endif
+			high_tables_size = HIGH_TABLES_SIZE * 1024;
+		}
+#endif
+	}
+
+#if CONFIG_GFXUMA == 1
+	add_uma_resource(dev, 7);
+#endif
+
+	for(link = dev->link_list; link; link = link->next) {
+		if (link->children) {
+			assign_resources(link);
+		}
+	}
+}
+
+static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
+{
+	u32 reg;
+	int i;
+	struct bus *link;
+	/* Unmap all of the HT chains */
+	for (reg = 0xe0; reg <= 0xec; reg += 4) {
+		f1_write_config32(reg, 0);
+	}
+#if CONFIG_EXT_CONF_SUPPORT == 1
+	// all nodes
+	for (i = 0; i< sysconf.nodes; i++) {
+		int index;
+		for(index = 0; index < 64; index++) {
+			pci_write_config32(__f1_dev[i], 0x110, index | (6<<28));
+			pci_write_config32(__f1_dev[i], 0x114, 0);
+		}
+
+	}
+#endif
+
+
+	for (link = dev->link_list; link; link = link->next) {
+		max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max);
+	}
+
+	/* Tune the hypertransport transaction for best performance.
+	 * Including enabling relaxed ordering if it is safe.
+	 */
+	get_fx_devs();
+	for (i = 0; i < fx_devs; i++) {
+		device_t f0_dev;
+		f0_dev = __f0_dev[i];
+		if (f0_dev && f0_dev->enabled) {
+			u32 httc;
+			httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
+			httc &= ~HTTC_RSP_PASS_PW;
+			if (!dev->link_list->disable_relaxed_ordering) {
+				httc |= HTTC_RSP_PASS_PW;
+			}
+			printk(BIOS_SPEW, "%s passpw: %s\n",
+				dev_path(dev),
+				(!dev->link_list->disable_relaxed_ordering)?
+				"enabled":"disabled");
+			pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
+		}
+	}
+	return max;
+}
+
+
+static struct device_operations pci_domain_ops = {
+	.read_resources	  = amdfam10_domain_read_resources,
+	.set_resources	  = amdfam10_domain_set_resources,
+	.enable_resources = amdfam10_domain_enable_resources,
+	.init		  = NULL,
+	.scan_bus	  = amdfam10_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+
+static void sysconf_init(device_t dev) // first node
+{
+	sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
+	sysconf.segbit = 0;
+	sysconf.ht_c_num = 0;
+
+	unsigned ht_c_index;
+
+	for (ht_c_index=0; ht_c_index<32; ht_c_index++) {
+		sysconf.ht_c_conf_bus[ht_c_index] = 0;
+	}
+
+	sysconf.nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
+
+	/* Find the bootstrap processors apicid */
+	sysconf.bsp_apicid = lapicid();
+}
+
+static void add_more_links(device_t dev, unsigned total_links)
+{
+	struct bus *link, *last = NULL;
+	int link_num;
+
+	for (link = dev->link_list; link; link = link->next)
+		last = link;
+
+	if (last) {
+		int links = total_links - last->link_num;
+		link_num = last->link_num;
+		if (links > 0) {
+			link = malloc(links*sizeof(*link));
+			if (!link)
+				die("Couldn't allocate more links!\n");
+			memset(link, 0, links*sizeof(*link));
+			last->next = link;
+		}
+	}
+	else {
+		link_num = -1;
+		link = malloc(total_links*sizeof(*link));
+		memset(link, 0, total_links*sizeof(*link));
+		dev->link_list = link;
+	}
+
+	for (link_num = link_num + 1; link_num < total_links; link_num++) {
+		link->link_num = link_num;
+		link->dev = dev;
+		link->next = link + 1;
+		last = link;
+		link = link->next;
+	}
+	last->next = NULL;
+}
+
+/* dummy read_resources */
+static void lapic_read_resources(device_t dev)
+{
+}
+
+static struct device_operations lapic_ops = {
+        .read_resources   = lapic_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .init             = 0,
+        .scan_bus         = 0,
+        .enable           = 0,
+        .ops_pci          = 0,
+};
+
+static u32 cpu_bus_scan(device_t dev, u32 max)
+{
+	struct bus *cpu_bus;
+	device_t dev_mc;
+#if CONFIG_CBB
+	device_t pci_domain;
+#endif
+	int i,j;
+	int nodes;
+	unsigned nb_cfg_54;
+	unsigned siblings;
+	int cores_found;
+	int disable_siblings;
+	unsigned ApicIdCoreIdSize;
+
+	nb_cfg_54 = 0;
+	ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
+	if (ApicIdCoreIdSize) {
+		siblings = (1<<ApicIdCoreIdSize)-1;
+	} else {
+		siblings = 3; //quad core
+	}
+
+	disable_siblings = !CONFIG_LOGICAL_CPUS;
+#if CONFIG_LOGICAL_CPUS == 1
+	get_option(&disable_siblings, "multi_core");
+#endif
+
+	// How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
+	nb_cfg_54 = read_nb_cfg_54();
+
+#if CONFIG_CBB
+	dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
+	if (dev_mc && dev_mc->bus) {
+		printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
+		pci_domain = dev_mc->bus->dev;
+		if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+			printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
+			dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
+			printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
+
+		} else {
+			printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	if (!dev_mc) {
+		dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+		if (dev_mc && dev_mc->bus) {
+			printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
+			pci_domain = dev_mc->bus->dev;
+			if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+				if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
+					printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
+					dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
+					printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
+					while (dev_mc) {
+						printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
+						dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
+						printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
+						dev_mc = dev_mc->sibling;
+					}
+				}
+			}
+		}
+	}
+
+#endif
+
+	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	if (!dev_mc) {
+		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+		die("");
+	}
+
+	sysconf_init(dev_mc);
+
+	nodes = sysconf.nodes;
+
+#if CONFIG_CBB && (NODE_NUMS > 32)
+	if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe
+		if (pci_domain->link_list && !pci_domain->link_list->next) {
+			struct bus *new_link = new_link(pci_domain);
+			pci_domain->link_list->next = new_link;
+			new_link->link_num = 1;
+			new_link->dev = pci_domain;
+			new_link->children = 0;
+			printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
+		}
+		pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
+	}
+#endif
+	/* Find which cpus are present */
+	cpu_bus = dev->link_list;
+	for (i = 0; i < nodes; i++) {
+		device_t cdb_dev, cpu;
+		struct device_path cpu_path;
+		unsigned busn, devn;
+		struct bus *pbus;
+
+		busn = CONFIG_CBB;
+		devn = CONFIG_CDB+i;
+		pbus = dev_mc->bus;
+#if CONFIG_CBB && (NODE_NUMS > 32)
+		if (i>=32) {
+			busn--;
+			devn-=32;
+			pbus = pci_domain->link_list->next);
+		}
+#endif
+
+		/* Find the cpu's pci device */
+		cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
+		if (!cdb_dev) {
+			/* If I am probing things in a weird order
+			 * ensure all of the cpu's pci devices are found.
+			 */
+			int fn;
+			for(fn = 0; fn <= 5; fn++) { //FBDIMM?
+				cdb_dev = pci_probe_dev(NULL, pbus,
+					PCI_DEVFN(devn, fn));
+			}
+			cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
+		}
+		if (cdb_dev) {
+			/* Ok, We need to set the links for that device.
+			 * otherwise the device under it will not be scanned
+			 */
+			int linknum;
+#if CONFIG_HT3_SUPPORT==1
+			linknum = 8;
+#else
+			linknum = 4;
+#endif
+			add_more_links(cdb_dev, linknum);
+		}
+
+		cores_found = 0; // one core
+		cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
+		if (cdb_dev && cdb_dev->enabled) {
+			j = pci_read_config32(cdb_dev, 0xe8);
+			cores_found = (j >> 12) & 3; // dev is func 3
+			if (siblings > 3)
+				cores_found |= (j >> 13) & 4;
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cdb_dev), cores_found);
+		}
+
+		u32 jj;
+		if (disable_siblings) {
+			jj = 0;
+		} else {
+			jj = cores_found;
+		}
+
+		for (j = 0; j <=jj; j++ ) {
+			extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
+			u32 modules = TopologyConfiguration.PlatformNumberOfModules;
+			u32 lapicid_start = 0;
+
+			/* Build the cpu device path */
+			cpu_path.type = DEVICE_PATH_APIC;
+			/*
+			 * APIC ID calucation is tightly coupled with AGESA v5 code.
+			 * This calculation MUST match the assignment calculation done
+			 * in LocalApicInitializationAtEarly() function.
+			 * And reference GetLocalApicIdForCore()
+			 *
+			 * Apply apic enumeration rules
+			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+			 * put the local-APICs at m..z
+			 * For systems with < 16 APICs, put the Local-APICs at 0..n and
+			 * put the IO-APICs at (n + 1)..z
+			 */
+			if (nodes * (cores_found + 1) >= 0x10) {
+  				lapicid_start = 0x10;
+			}
+			cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j);
+
+			/* See if I can find the cpu */
+			cpu = find_dev_path(cpu_bus, &cpu_path);
+
+			/* Enable the cpu if I have the processor */
+			if (cdb_dev && cdb_dev->enabled) {
+				if (!cpu) {
+					cpu = alloc_dev(cpu_bus, &cpu_path);
+				}
+				if (cpu) {
+					cpu->enabled = 1;
+				}
+			}
+
+			/* Disable the cpu if I don't have the processor */
+			if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
+				cpu->enabled = 0;
+			}
+
+			/* Report what I have done */
+			if (cpu) {
+				cpu->path.apic.node_id = i;
+				cpu->path.apic.core_id = j;
+				if (cpu->path.type == DEVICE_PATH_APIC) {
+					cpu->ops = &lapic_ops;
+				}
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
+					dev_path(cpu), cpu->enabled?"enabled":"disabled");
+			}
+
+		} //j
+	}
+	return max;
+}
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static void cpu_bus_read_resources(device_t dev)
+{
+#if CONFIG_MMCONF_SUPPORT
+	struct resource *resource = new_resource(dev, 0xc0010058);
+	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
+#endif
+}
+
+static void cpu_bus_set_resources(device_t dev)
+{
+	struct resource *resource = find_resource(dev, 0xc0010058);
+	if (resource) {
+		report_resource_stored(dev, resource, " <mmconfig>");
+	}
+	pci_dev_set_resources(dev);
+}
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources	  = cpu_bus_read_resources,
+	.set_resources	  = cpu_bus_set_resources,
+	.enable_resources = cpu_bus_noop,
+	.init		  = cpu_bus_init,
+	.scan_bus	  = cpu_bus_scan,
+};
+
+static void root_complex_enable_dev(struct device *dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	}
+	else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_amd_agesa_family10_root_complex_ops = {
+	CHIP_NAME("AMD FAM10 Root Complex")
+	.enable_dev = root_complex_enable_dev,
+};
+
diff --git a/src/northbridge/amd/agesa/family10/northbridge.h b/src/northbridge/amd/agesa/family10/northbridge.h
new file mode 100755
index 0000000000..0530ee7495
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM10H_H
+#define NORTHBRIDGE_AMD_AGESA_FAM10H_H
+
+static struct device_operations pci_domain_ops;
+static struct device_operations cpu_bus_ops;
+
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM10H_H */
diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h
new file mode 100755
index 0000000000..5b24f2d63a
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/reset_test.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ * copy from src/northbridge/amd/amdfam10/reset_test.c
+ */
+
+#ifndef _RESET_TEST_H_
+#define _RESET_TEST_H_
+
+#include "amdfam10.h"	/* NODE_PCI */
+
+#define NODE_ID			0x60
+#define HT_INIT_CONTROL		0x6c
+#define HTIC_ColdR_Detect	(1<<4)
+#define HTIC_BIOSR_Detect	(1<<5)
+#define HTIC_INIT_Detect	(1<<6)
+
+static inline u32 warm_reset_detect(u8 nodeid)
+{
+	u32 htic;
+	device_t device;
+	device = NODE_PCI(nodeid, 0);
+	htic = pci_io_read_config32(device, HT_INIT_CONTROL);
+	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
+}
+
+static inline void distinguish_cpu_resets(u8 nodeid)
+{
+	u32 htic;
+	device_t device;
+	device = NODE_PCI(nodeid, 0);
+	htic = pci_io_read_config32(device, HT_INIT_CONTROL);
+	htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
+	pci_io_write_config32(device, HT_INIT_CONTROL, htic);
+}
+
+#endif
diff --git a/src/northbridge/amd/agesa/family10/root_complex/Kconfig b/src/northbridge/amd/agesa/family10/root_complex/Kconfig
new file mode 100755
index 0000000000..345896b171
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/root_complex/Kconfig
@@ -0,0 +1,2 @@
+config NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
+	bool
diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h
new file mode 100755
index 0000000000..15a2e1ae69
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/root_complex/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_amd_agesa_family10_root_complex_config
+{
+};
+
+extern struct chip_operations northbridge_amd_agesa_family10_root_complex_ops;
diff --git a/src/northbridge/amd/agesa/family10/ssdt.asl b/src/northbridge/amd/agesa/family10/ssdt.asl
new file mode 100755
index 0000000000..e637f1f094
--- /dev/null
+++ b/src/northbridge/amd/agesa/family10/ssdt.asl
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file
+ */
+
+DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM15H", "AMD-ACPI", 0x1000)
+{
+	/*
+	 * These objects were referenced but not defined in this table
+	 */
+	External (\_SB_.PCI0, DeviceObj)
+
+	Scope (\_SB.PCI0)
+	{
+		Name (BUSN, Package (0x20) /* HC_NUMS */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x10101010,
+			0x11111111,
+			0x12121212,
+			0x13131313,
+			0x14141414,
+			0x15151515,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc
+		})
+		Name (MMIO, Package (0x80) /* HC_NUMS * 4 */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x11111111,
+			0x22222222,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888
+		})
+		Name (PCIO, Package (0x40) /* HC_NUMS * 2 */
+		{
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0xaaaaaaaa,
+			0xbbbbbbbb,
+			0xcccccccc,
+			0xdddddddd,
+			0xeeeeeeee,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x99999999,
+			0xaaaaaaaa,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444
+		})
+		Name (SBLK, 0x11)
+		Name (TOM1, 0xaaaaaaaa)
+		Name (SBDN, 0xbbbbbbbb)
+		Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888
+		})
+		Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */
+		{
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888,
+			0x11111111,
+			0x22222222,
+			0x33333333,
+			0x44444444,
+			0x55555555,
+			0x66666666,
+			0x77777777,
+			0x88888888
+		})
+		Name (CBB, 0x99)
+		Name (CBST, 0x88)
+		Name (CBB2, 0x77)
+		Name (CBS2, 0x66)
+
+	}
+}
+