remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

14 files changed, 10 insertions, 10 deletions

diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h
index e6f9d81b83..e6f9d81b83 100755..100644
--- a/src/northbridge/amd/agesa/family10/amdfam10.h
+++ b/src/northbridge/amd/agesa/family10/amdfam10.h
diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
index f6ae8be8b9..f6ae8be8b9 100755..100644
--- a/src/northbridge/amd/agesa/family10/bootblock.c
+++ b/src/northbridge/amd/agesa/family10/bootblock.c
diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h
index c0ac56e5a9..c0ac56e5a9 100755..100644
--- a/src/northbridge/amd/agesa/family10/chip.h
+++ b/src/northbridge/amd/agesa/family10/chip.h
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index b3e4c63d00..b3e4c63d00 100755..100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
diff --git a/src/northbridge/amd/agesa/family10/northbridge.h b/src/northbridge/amd/agesa/family10/northbridge.h
index 0530ee7495..0530ee7495 100755..100644
--- a/src/northbridge/amd/agesa/family10/northbridge.h
+++ b/src/northbridge/amd/agesa/family10/northbridge.h
diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h
index 5b24f2d63a..5b24f2d63a 100755..100644
--- a/src/northbridge/amd/agesa/family10/reset_test.h
+++ b/src/northbridge/amd/agesa/family10/reset_test.h
diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h
index 15a2e1ae69..15a2e1ae69 100755..100644
--- a/src/northbridge/amd/agesa/family10/root_complex/chip.h
+++ b/src/northbridge/amd/agesa/family10/root_complex/chip.h
diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
index 6ec4da9c9f..6ec4da9c9f 100755..100644
--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c
+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c
index eead31d26b..f6ae8be8b9 100755..100644
--- a/src/northbridge/amd/agesa/family12/bootblock.c
+++ b/src/northbridge/amd/agesa/family12/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
diff --git a/src/northbridge/amd/agesa/family12/chip.h b/src/northbridge/amd/agesa/family12/chip.h
index 462610d6ea..462610d6ea 100755..100644
--- a/src/northbridge/amd/agesa/family12/chip.h
+++ b/src/northbridge/amd/agesa/family12/chip.h
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 55109b57be..2c039d2b4e 100755..100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -311,7 +311,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
         }
 
 #if 0
-        // We need to double check if there is speical set on base reg and limit reg 
+        // We need to double check if there is speical set on base reg and limit reg
             // are not continous instead of hole, it will find out it's hole_startk
         if(mem_hole.node_id==-1) {
             resource_t limitk_pri = 0;
@@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
             }
         }
 #endif
-        
+
         return mem_hole;
 }
 #endif
@@ -471,7 +471,7 @@ static void set_resources(device_t dev)
     struct resource *res;
 
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resources - Start.\n");
- 
+
     /* Find the nodeid */
     nodeid = amdfam12_nodeid(dev);
 
@@ -782,7 +782,7 @@ static void domain_enable_resources(device_t dev)
   /* Must be called after PCI enumeration and resource allocation */
 //  printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - Start.\n");
   printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - Start.\n");
-//  val = agesawrapper_amdinitmid (); 
+//  val = agesawrapper_amdinitmid ();
 //  if(val) {
 //    printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
 //  }
@@ -819,7 +819,7 @@ static void cpu_bus_set_resources(device_t dev)
     pci_dev_set_resources(dev);
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_set_resources - End.\n");
 }
- 
+
 static void cpu_bus_init(device_t dev)
 {
     u32 val;
@@ -830,20 +830,20 @@ static void cpu_bus_init(device_t dev)
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - Start.\n");
-    sb_After_Pci_Init (); 
+    sb_After_Pci_Init ();
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - Start.\n");
-    sb_Mid_Post_Init (); 
+    sb_Mid_Post_Init ();
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - Start.\n");
-    val = agesawrapper_amdinitmid (); 
+    val = agesawrapper_amdinitmid ();
     if(val) {
         printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
     }
diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h
index 8de80ff501..8de80ff501 100755..100644
--- a/src/northbridge/amd/agesa/family12/northbridge.h
+++ b/src/northbridge/amd/agesa/family12/northbridge.h
diff --git a/src/northbridge/amd/agesa/family12/root_complex/chip.h b/src/northbridge/amd/agesa/family12/root_complex/chip.h
index 91599252fc..91599252fc 100755..100644
--- a/src/northbridge/amd/agesa/family12/root_complex/chip.h
+++ b/src/northbridge/amd/agesa/family12/root_complex/chip.h
diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
index eead31d26b..f6ae8be8b9 100644
--- a/src/northbridge/amd/agesa/family14/bootblock.c
+++ b/src/northbridge/amd/agesa/family14/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>