diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-26 11:56:43 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-10-06 05:35:35 +0000 |
| commit | 2b9f5b5c121997e34743adf6fbe6b03676805404 (patch) | |
| tree | 10fdad98db7cb6ef8bcc4fe907cfa929232d9205 /src/northbridge/amd/agesa | |
| parent | 8269096bd9c6d1aae85de1eb3481f8b94b4e8278 (diff) | |
AGESA f16kb: Enable MRC cache equivalent fastboot
Try restoring previous memory training results from SPI flash
to improve raminit speed.
Change-Id: I6f4c2342e2eea6c1ecfb71da8564225b6230f51e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/amd/agesa')
| -rw-r--r-- | src/northbridge/amd/agesa/family16kb/state_machine.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 8457d832d7..00a7e85265 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -30,6 +30,13 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { + AGESA_STATUS status; + + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { + status = OemInitResume(&Post->MemConfig.MemContext); + if (AGESA_SUCCESS == status) + Post->MemConfig.MemRestoreCtl = 1; + } } void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |