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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-06-27 23:14:51 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-28 00:23:39 +0000 |
| commit | 27e1801ea79b591f8a34591bc1a3576dd66406ba (patch) | |
| tree | 6195074ef4a3aa06ad9b9ab64b4dd4f5c20ecafb /src/northbridge/amd/agesa/family15tn/northbridge.c | |
| parent | 168ef399c43ad79a40a8bbb2de921a2bd906b3f5 (diff) | |
northbridge/amd/agesa/*: Add whitespace around '<<'
Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn/northbridge.c')
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 95787fc867..66da338b94 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -65,12 +65,12 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -80,10 +80,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -93,7 +93,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -172,7 +172,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -663,7 +663,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } |