AMD Fam15: Add SPD read functions to wrapper code

Change:
This is the initial step for moving the AMD F15 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper.  The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories.  The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.

Notes:
This started by duplicating what was in Dinar, and was changed to
use the devicetree.cb structures.  Significant cleanup and magic
number reduction was done as well.

It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.

This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
and move the SMBus initialization and access into the southbridge
wrapper.  Maybe that can come next.

Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2777
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 49 insertions, 0 deletions

diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h
new file mode 100644
index 0000000000..66c44c4b06
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/chip.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _NB_AGESA_CHIP_H_
+#define _NB_AGESA_CHIP_H_
+
+struct northbridge_amd_agesa_family15_config
+{
+	/*
+	 * Here are a couple of examples of how this would be put into the
+	 * devicetree.cb file.  Note the array is oversized to support different
+	 * configurations of server boards.
+	 * This should be placed after the device pci 18.x statements.
+	 *
+	 * Example: AMD Dinar
+	 * register "spdAddrLookup" = "
+	 * { // Use 8-bit SPD addresses here
+	 * 	{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3
+	 * 	{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3
+	 * }"
+	 * Example: Tyan S8226
+	 * register "spdAddrLookup" = "
+	 * { // Use 8-bit SPD addresses here
+	 *  { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0
+	 *  { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1
+	 * }"
+	 *
+	 */
+
+	u8 spdAddrLookup[8][4][4];
+};
+
+#endif