northbridge/amd/agesa: Improve code formatting

Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 18 insertions, 18 deletions

diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
index 7afa39df03..3c91d2d97d 100644
--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c
+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
@@ -54,12 +54,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 
 	/* io range allocation */
 	tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
-	for (i=0; i<nodes; i++) {
+	for (i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 1);
 		pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
 	}
-	tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	     //base :ISA and VGA ?
-	for (i=0; i<nodes; i++){
+	tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4));	     //base :ISA and VGA ?
+	for (i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 1);
 		pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
 	}
@@ -73,7 +73,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 	device_t dev;
 
 	 /* io range allocation */
-	for (i=0; i<nodes; i++) {
+	for (i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 1);
 		pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
 		pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
@@ -87,7 +87,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn)
 #if 0
 	u32 index;
 
-	for (index=0; index<256; index++) {
+	for (index = 0; index < 256; index++) {
 		if (sysconf.conf_io_addrx[index+4] == 0) {
 			sysconf.conf_io_addr[index+4] =  (nodeid & 0x3f)  ;
 			sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
@@ -103,7 +103,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
 #if 0
 	u32 index;
 
-	for (index=0; index<64; index++) {
+	for (index = 0; index < 64; index++) {
 		if (sysconf.conf_mmio_addrx[index+8] == 0) {
 			sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
 			sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
@@ -124,7 +124,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 	tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
 	pci_write_config32(__f1_dev[0], reg+4, tempreg);
 
-	tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
+	tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
 #if 0
 	// FIXME: can we use VGA reg instead?
 	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 15269727d8..f89c2cc17e 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -41,7 +41,7 @@ static device_t __f0_dev[FX_DEVS];
 static device_t __f1_dev[FX_DEVS];
 static device_t __f2_dev[FX_DEVS];
 static device_t __f4_dev[FX_DEVS];
-static unsigned fx_devs=0;
+static unsigned fx_devs = 0;
 
 static device_t get_node_pci(u32 nodeid, u32 fn)
 {
@@ -136,10 +136,10 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
 	result = 2;
 	if (res) {
 		result = 0;
-		if (    (goal_link == (link - 1)) &&
-			 (goal_nodeid == (nodeid - 1)) &&
-			 (res->flags <= 1)) {
-				result = 1;
+		if ((goal_link == (link - 1)) &&
+		    (goal_nodeid == (nodeid - 1)) &&
+		    (res->flags <= 1)) {
+			result = 1;
 		}
 	}
 	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
@@ -397,10 +397,10 @@ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
 			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
 					link->secondary,link->subordinate);
 			/* We need to make sure the vga_pri is under the link */
-			if ((vga_pri->bus->secondary >= link->secondary ) &&
-				(vga_pri->bus->secondary <= link->subordinate ))
+			if ((vga_pri->bus->secondary >= link->secondary) &&
+			    (vga_pri->bus->secondary <= link->subordinate))
 #endif
-					break; // XXX this break looks questionable
+				break; // XXX this break looks questionable
 		}
 	}
 
@@ -485,7 +485,7 @@ static void domain_read_resources(device_t dev)
 		if ((base & 3) != 0) {
 			unsigned nodeid, reg_link;
 			device_t reg_dev;
-			if (reg<0xc0) { // mmio
+			if (reg < 0xc0) { // mmio
 				nodeid = (limit & 0xf) + (base&0x30);
 			} else { // io
 				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
@@ -604,11 +604,11 @@ static void domain_set_resources(device_t dev)
 			 mmio_basek, basek, limitk);
 
 		/* split the region to accommodate pci memory space */
-		if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+		if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
 			if (basek <= mmio_basek) {
 				unsigned pre_sizek;
 				pre_sizek = mmio_basek - basek;
-				if (pre_sizek>0) {
+				if (pre_sizek > 0) {
 					ram_resource(dev, idx, basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;