diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-14 08:30:17 +0200 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-19 19:28:00 +0100 |
commit | ac7402dc11337c31c51a8209f005e2dfd6861849 (patch) | |
tree | d3c9c6d21b8218943648fc3fb0c7d870a0228e7e /src/northbridge/amd/agesa/family12 | |
parent | 2fa088be40fc2073ae2b68b0407f1faabe81ee2b (diff) |
AGESA fam12 fam14: Drop EXT_CONF_SUPPORT
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped
from other AGESA families.
Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family12')
-rw-r--r-- | src/northbridge/amd/agesa/family12/amdfam12_conf.c | 213 | ||||
-rw-r--r-- | src/northbridge/amd/agesa/family12/northbridge.c | 20 |
2 files changed, 34 insertions, 199 deletions
diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 00ff641c8d..431cf2c198 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -48,67 +48,6 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -#if CONFIG_EXT_CONF_SUPPORT -static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, - u32 busn_min, u32 busn_max, - u32 type) -{ - device_t dev; - u32 i; - u32 tempreg; - u32 index_min, index_max; - u32 dest_min, dest_max; - index_min = busn_min>>2; dest_min = busn_min - (index_min<<2); - index_max = busn_max>>2; dest_max = busn_max - (index_max<<2); - - // three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max -#if defined(__PRE_RAM__) - dev = NODE_PCI(nodeid, 1); -#else - dev = __f1_dev[nodeid]; -#endif // defined(__PRE_RAM__) - if(index_min== index_max) { - pci_write_config32(dev, 0x110, index_min | (type<<28)); - tempreg = pci_read_config32(dev, 0x114); - for(i=dest_min; i<=dest_max; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again - pci_write_config32(dev, 0x114, tempreg); - } else if(index_min<index_max) { - pci_write_config32(dev, 0x110, index_min | (type<<28)); - tempreg = pci_read_config32(dev, 0x114); - for(i=dest_min; i<=3; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again - pci_write_config32(dev, 0x114, tempreg); - - pci_write_config32(dev, 0x110, index_max | (type<<28)); - tempreg = pci_read_config32(dev, 0x114); - for(i=0; i<=dest_max; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again - pci_write_config32(dev, 0x114, tempreg); - if((index_max-index_min)>1) { - tempreg = 0; - for(i=0; i<=3; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - for(i=index_min+1; i<index_max;i++) { - pci_write_config32(dev, 0x110, i | (type<<28)); - pci_write_config32(dev, 0x114, tempreg); - } - } - } -} -#endif // CONFIG_EXT_CONF_SUPPORT - #if defined(__PRE_RAM__) static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) @@ -117,43 +56,17 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 tempreg; device_t dev; -#if CONFIG_EXT_CONF_SUPPORT - if(ht_c_index<4) { -#endif - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for(i=0; i<nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); - } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for(i=0; i<nodes; i++){ - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); - } -#if CONFIG_EXT_CONF_SUPPORT - return; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for(i=0; i<nodes; i++) { + dev = NODE_PCI(i, 1); + pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - - u32 cfg_map_dest; - u32 j; - - // if ht_c_index > 3, We should use extend space - - if(io_min>io_max) return; - - // for nodeid at first - cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0); - - set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4); - - // all other nodes - cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0); - for(j = 0; j< nodes; j++) { - if(j== nodeid) continue; - set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4); + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + for(i=0; i<nodes; i++){ + dev = NODE_PCI(i, 1); + pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } -#endif // CONFIG_EXT_CONF_SUPPORT } @@ -162,29 +75,13 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; device_t dev; -#if CONFIG_EXT_CONF_SUPPORT - if(ht_c_index<4) { -#endif - /* io range allocation */ - for(i=0; i<nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); - pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); - } -#if CONFIG_EXT_CONF_SUPPORT - return; - } - // : if hc_c_index > 3, We should use io_min, io_max to clear extend space - u32 cfg_map_dest; - u32 j; - - // all nodes - cfg_map_dest = 0; - for(j = 0; j< nodes; j++) { - set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4); + /* io range allocation */ + for(i=0; i<nodes; i++) { + dev = NODE_PCI(i, 1); + pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); + pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); } -#endif } #endif // defined(__PRE_RAM__) @@ -227,39 +124,23 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, { u32 tempreg; -#if CONFIG_EXT_CONF_SUPPORT - if(reg!=0x110) { -#endif - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif - pci_write_config32(__f1_dev[0], reg, tempreg); -#if CONFIG_EXT_CONF_SUPPORT - return; + // FIXME: can we use VGA reg instead? + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; } - - u32 cfg_map_dest; - u32 j; - // if ht_c_index > 3, We should use extend space - if(io_min>io_max) return; - // for nodeid at first - cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0); - - set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4); -#endif // CONFIG_EXT_CONF_SUPPORT + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + pci_write_config32(__f1_dev[0], reg, tempreg); } @@ -267,39 +148,11 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi { u32 tempreg; -#if CONFIG_EXT_CONF_SUPPORT - if(reg!=0x110) { -#endif - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -#if CONFIG_EXT_CONF_SUPPORT - return; - } - - device_t dev; - u32 j; - // if ht_c_index > 3, We should use extend space - // for nodeid at first - u32 enable; - - if(mmio_min>mmio_max) { - return; - } - - enable = 1; - - dev = __f1_dev[nodeid]; - tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0); - pci_write_config32(dev, 0x110, index | (2<<28)); - pci_write_config32(dev, 0x114, tempreg); - - tempreg = ((mmio_max>>3) & 0x1fffff00) | enable; - pci_write_config32(dev, 0x110, index | (3<<28)); - pci_write_config32(dev, 0x114, tempreg); -#endif // CONFIG_EXT_CONF_SUPPORT + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + pci_write_config32(__f1_dev[0], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + pci_write_config32(__f1_dev[0], reg, tempreg); } #endif // !defined(__PRE_RAM__) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 8d82925152..f8256bb25c 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -225,13 +225,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam12_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if CONFIG_EXT_CONF_SUPPORT - if((resource->index & 0x1fff) == 0x1110) { // ext - align = 8; - } - else -#endif - align = log2(HT_IO_HOST_ALIGN); + align = log2(HT_IO_HOST_ALIGN); resource->base = 0; resource->size = 0; resource->align = align; @@ -250,13 +244,6 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; - -#if CONFIG_EXT_CONF_SUPPORT - if((resource->index & 0x1fff) == 0x1110) { // ext - normalize_resource(resource); - } -#endif - } /* Initialize the memory constraints on the current bus */ @@ -268,11 +255,6 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT - if((resource->index & 0x1fff) == 0x1110) { // ext - normalize_resource(resource); - } -#endif } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } |