AGESA: Add amd_initcpuio() and amd_initmmio()

These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().

Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

2 files changed, 1 insertions, 94 deletions

diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c
index f6ae45c3f1..d9c5d37b87 100644
--- a/src/northbridge/amd/agesa/family12/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family12/agesawrapper.c
@@ -45,99 +45,6 @@ VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
 VOID *AcpiAlib = NULL;
 
-AGESA_STATUS agesawrapper_amdinitcpuio(VOID)
-{
-	UINT64 MsrReg;
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
-	AMD_CONFIG_PARAMS StdHeader;
-
-	/* Enable MMIO on AMD CPU Address Map Controller */
-
-	/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
-	PciData = 0x00000B00;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
-	PciData = 0x00000A03;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Set TOM-DFFFFFFF to Node0 Link0. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
-	PciData = 0x00DFFF00;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
-	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32) MsrReg;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC);
-	PciData = 0x00FFFF00 | 0x80;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8);
-	PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
-//-  PciData = 0x0000F000;
-	PciData = 0x00FFF000;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
-	PciData = 0x00000013;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	return AGESA_SUCCESS;
-}
-
-AGESA_STATUS agesawrapper_amdinitmmio(VOID)
-{
-	UINT64 MsrReg;
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
-	AMD_CONFIG_PARAMS StdHeader;
-
-	/*
-	   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-	   Address MSR register.
-	 */
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
-
-	/*
-	   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-	 */
-	LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
-	MsrReg = MsrReg | 0x0000400000000000ull;
-	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
-
-	/* Enable Non-Post Memory in CPU */
-	PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
-	PciData = (PciData >> 8) & ~0xff;
-	PciData |= 0x80;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA0);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Enable memory access */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
-	LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
-	PciData |= BIT1;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
-	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
-	LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
-	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
-
-	return AGESA_SUCCESS;
-}
-
 AGESA_STATUS agesawrapper_amdinitreset(VOID)
 {
 	AGESA_STATUS status;
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index f8256bb25c..fe9cd72032 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -756,7 +756,7 @@ static void domain_enable_resources(device_t dev)
 #endif
 
 	/* Enable MMIO on AMD CPU Address Map Controller */
-	agesawrapper_amdinitcpuio();
+	amd_initcpuio();
 
 	agesawrapper_amdinitmid();
 	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);