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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-14 08:30:17 +0200 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-19 19:28:00 +0100 |
commit | ac7402dc11337c31c51a8209f005e2dfd6861849 (patch) | |
tree | d3c9c6d21b8218943648fc3fb0c7d870a0228e7e /src/northbridge/amd/agesa/family10 | |
parent | 2fa088be40fc2073ae2b68b0407f1faabe81ee2b (diff) |
AGESA fam12 fam14: Drop EXT_CONF_SUPPORT
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped
from other AGESA families.
Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family10')
-rw-r--r-- | src/northbridge/amd/agesa/family10/northbridge.c | 234 |
1 files changed, 27 insertions, 207 deletions
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 2c46129a84..2b2dad5530 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -57,23 +57,12 @@ static device_t __f2_dev[NODE_NUMS]; static device_t __f4_dev[NODE_NUMS]; static unsigned fx_devs = 0; -#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 -#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! -#endif - static dram_base_mask_t get_dram_base_mask(u32 nodeid) { device_t dev; dram_base_mask_t d; dev = __f1_dev[0]; -#if CONFIG_EXT_CONF_SUPPORT - /* I will use ext space only for simple */ - pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] - d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 - pci_write_config32(dev, 0x110, nodeid | (0<<28)); - d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8]; -#else u32 temp; temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too @@ -86,67 +75,9 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] d.base |= temp<<21; -#endif return d; } -#if CONFIG_EXT_CONF_SUPPORT -static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, - u32 busn_min, u32 busn_max, - u32 type) -{ - device_t dev; - u32 i; - u32 tempreg; - u32 index_min, index_max; - u32 dest_min, dest_max; - index_min = busn_min>>2; dest_min = busn_min - (index_min<<2); - index_max = busn_max>>2; dest_max = busn_max - (index_max<<2); - - // three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max - dev = __f1_dev[nodeid]; - if (index_min== index_max) { - pci_write_config32(dev, 0x110, index_min | (type<<28)); - tempreg = pci_read_config32(dev, 0x114); - for (i=dest_min; i<=dest_max; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again - pci_write_config32(dev, 0x114, tempreg); - } else if (index_min<index_max) { - pci_write_config32(dev, 0x110, index_min | (type<<28)); - tempreg = pci_read_config32(dev, 0x114); - for (i=dest_min; i<=3; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again - pci_write_config32(dev, 0x114, tempreg); - - pci_write_config32(dev, 0x110, index_max | (type<<28)); - tempreg = pci_read_config32(dev, 0x114); - for (i=0; i<=dest_max; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again - pci_write_config32(dev, 0x114, tempreg); - if ((index_max-index_min)>1) { - tempreg = 0; - for (i=0; i<=3; i++) { - tempreg &= ~(0xff<<(i*8)); - tempreg |= (cfg_map_dest<<(i*8)); - } - for (i=index_min+1; i<index_max;i++) { - pci_write_config32(dev, 0x110, i | (type<<28)); - pci_write_config32(dev, 0x114, tempreg); - } - } - } -} -#endif - #if CONFIG_PCI_BUS_SEGN_BITS static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) @@ -204,16 +135,8 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 io_min, u32 io_max) { u32 val; -#if CONFIG_EXT_CONF_SUPPORT - if (reg!=0x110) { -#endif - /* io range allocation */ - index = (reg-0xc0)>>3; -#if CONFIG_EXT_CONF_SUPPORT - } else { - index+=4; - } -#endif + /* io range allocation */ + index = (reg-0xc0)>>3; val = (nodeid & 0x3f); // 6 bits used sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid @@ -228,16 +151,8 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { u32 val; -#if CONFIG_EXT_CONF_SUPPORT - if (reg!=0x110) { -#endif - /* io range allocation */ - index = (reg-0x80)>>3; -#if CONFIG_EXT_CONF_SUPPORT - } else { - index += 8; - } -#endif + /* io range allocation */ + index = (reg-0x80)>>3; val = (nodeid & 0x3f) ; // 6 bits used sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn @@ -254,48 +169,26 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 i; u32 tempreg; -#if CONFIG_EXT_CONF_SUPPORT - if (reg!=0x110) { -#endif - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -#if CONFIG_EXT_CONF_SUPPORT - return; + // FIXME: can we use VGA reg instead? + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; } - - u32 cfg_map_dest; - u32 j; - // if ht_c_index > 3, We should use extend space - if (io_min>io_max) return; - // for nodeid at first - cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0); - - set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4); - - // all other nodes - cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0); - for (j = 0; j< sysconf.nodes; j++) { - if (j== nodeid) continue; - set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4); + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; } #endif + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); } static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) @@ -303,57 +196,14 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 i; u32 tempreg; -#if CONFIG_EXT_CONF_SUPPORT - if (reg!=0x110) { -#endif - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -#if CONFIG_EXT_CONF_SUPPORT - return; - } - - device_t dev; - u32 j; - // if ht_c_index > 3, We should use extend space - // for nodeid at first - u32 enable; - - if (mmio_min>mmio_max) { - return; - } - - enable = 1; - dev = __f1_dev[nodeid]; - tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0); - pci_write_config32(dev, 0x110, index | (2<<28)); - pci_write_config32(dev, 0x114, tempreg); - - tempreg = ((mmio_max>>3) & 0x1fffff00) | enable; - pci_write_config32(dev, 0x110, index | (3<<28)); - pci_write_config32(dev, 0x114, tempreg); - - // all other nodes - tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0); - for (j = 0; j< sysconf.nodes; j++) { - if (j== nodeid) continue; - dev = __f1_dev[j]; - pci_write_config32(dev, 0x110, index | (2<<28)); - pci_write_config32(dev, 0x114, tempreg); - } - tempreg = ((mmio_max>>3) & 0x1fffff00) | enable; - for (j = 0; j< sysconf.nodes; j++) { - if(j==nodeid) continue; - dev = __f1_dev[j]; - pci_write_config32(dev, 0x110, index | (3<<28)); - pci_write_config32(dev, 0x114, tempreg); - } -#endif + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); } static device_t get_node_pci(u32 nodeid, u32 fn) @@ -548,13 +398,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam10_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if CONFIG_EXT_CONF_SUPPORT - if((resource->index & 0x1fff) == 0x1110) { // ext - align = 8; - } - else -#endif - align = log2(HT_IO_HOST_ALIGN); + align = log2(HT_IO_HOST_ALIGN); resource->base = 0; resource->size = 0; resource->align = align; @@ -573,13 +417,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; - -#if CONFIG_EXT_CONF_SUPPORT - if ((resource->index & 0x1fff) == 0x1110) { // ext - normalize_resource(resource); - } -#endif - } /* Initialize the memory constraints on the current bus */ @@ -591,11 +428,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT - if ((resource->index & 0x1fff) == 0x1110) { // ext - normalize_resource(resource); - } -#endif } } @@ -1079,18 +911,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) for (reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } -#if CONFIG_EXT_CONF_SUPPORT - // all nodes - for (i = 0; i< sysconf.nodes; i++) { - int index; - for(index = 0; index < 64; index++) { - pci_write_config32(__f1_dev[i], 0x110, index | (6<<28)); - pci_write_config32(__f1_dev[i], 0x114, 0); - } - - } -#endif - for (link = dev->link_list; link; link = link->next) { max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); |