AMD Steppe Eagle: Add northbridge files for new SoC family

Add the northbridge file for AMD's new Mullins and Steppe Eagle
processor family.  Since the processor family name is not the
same across AMD's sales and marketing channels, I have elected
to use part of the processor ID as the family name.  The intent
is to reduce confusion since the processor ID is the same for
both families.  This northbridge support has only been validated
on the AMD Embedded variants ("Steppe Eagle").

The AGESA wrappers in coreboot have a function that is intended to
mirror the UMA memory allocation performed during memory initialization
by AGESA.  Update the Steppe Eagle memory allocation to mimic the
memory reservation done inside the AGESA BLOB.

Change the default CBMEM address, the default video BIOS device ID,
and a couple of other defaults to match changes in coreboot community
code.

The northbridge chip.h specifies how many processor sockets, how
many channels, and how many DIMM slots are supported by the
northbridge.  Steppe Eagle does not permit multisocket systems
and has only one memory controller channel.

Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6678
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>

3 files changed, 140 insertions, 0 deletions

diff --git a/src/northbridge/amd/agesa/common/Makefile.inc b/src/northbridge/amd/agesa/common/Makefile.inc
new file mode 100644
index 0000000000..d3d8087de5
--- /dev/null
+++ b/src/northbridge/amd/agesa/common/Makefile.inc
@@ -0,0 +1,23 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += ../../../../device/dram/ddr3.c
+romstage-y += common.c
+
+ramstage-y += common.c
diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c
new file mode 100644
index 0000000000..91c58e3bd8
--- /dev/null
+++ b/src/northbridge/amd/agesa/common/common.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "common.h"
+#include <device/dram/ddr3.h>
+#include <string.h>
+#include <cbfs.h>
+
+AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+#ifdef __PRE_RAM__
+	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+	size_t spd_file_length;
+
+	if (info->MemChannelId > CONFIG_AGESA_DDR3_CHANNEL_MAX)
+		return AGESA_ERROR;
+	if (info->SocketId != 0)
+		return AGESA_ERROR;
+	if (info->DimmId != 0)
+		return AGESA_ERROR;
+
+	char *spd_file;
+
+	spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", CBFS_TYPE_SPD_BIN, &spd_file_length);
+	if (!spd_file)
+		die("file [spd.bin] not found in CBFS");
+
+	printk(BIOS_DEBUG, "\nCBFS SPD file length = 0x%x bytes\n", (unsigned int)spd_file_length);
+
+	if (CONFIG_MULTIPLE_DDR_SPD) {
+		struct multi_spd_info *spd_info = (struct multi_spd_info *)info->Buffer;
+		printk(BIOS_DEBUG, "Multiple DDR SPD: using offset %d\n", spd_info->offset);
+		if (spd_info->offset > (spd_file_length / spd_info->size))
+			printk(BIOS_EMERG, "Multiple SPD offset is greater than SPD length\n");
+		else {
+			spd_file += spd_info->offset * spd_info->size;
+			spd_file_length = spd_info->size;
+		}
+	}
+	memcpy((char*)info->Buffer, spd_file, spd_file_length);
+
+	u16 crc = spd_ddr3_calc_crc(info->Buffer, spd_file_length);
+	if (crc == 0){
+		printk(BIOS_EMERG, "Error: Unable to calculate CRC on SPD\n");
+		return AGESA_UNSUPPORTED;
+	}
+	if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0))
+	  || (info->Buffer[SPD_CRC_LO] != (crc & 0xff))
+	  || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) {
+		printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
+		info->Buffer[SPD_CRC_LO] = crc & 0xff;
+		info->Buffer[SPD_CRC_HI] = crc >> 8;
+		u16 i;
+		printk(BIOS_SPEW, "\nDisplay the SPD");
+		for (i = 0; i < spd_file_length; i++) {
+			if((i % 16) == 0x00)
+				printk(BIOS_SPEW, "\n%02x:  ",i);
+			printk(BIOS_SPEW, "%02x ", info->Buffer[i]);
+		}
+		printk(BIOS_SPEW, "\n");
+	}
+	return AGESA_SUCCESS;
+#else
+	return AGESA_UNSUPPORTED;
+#endif
+}
diff --git a/src/northbridge/amd/agesa/common/common.h b/src/northbridge/amd/agesa/common/common.h
new file mode 100644
index 0000000000..f60091a181
--- /dev/null
+++ b/src/northbridge/amd/agesa/common/common.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESA_COMMON_H_
+#define _AGESA_COMMON_H_
+
+#define SPD_CRC_HI  127
+#define SPD_CRC_LO  126
+
+struct  multi_spd_info {
+	u8 offset;  // defines spd 0,1,...
+	u8 size;    // defines spd size
+};
+
+AGESA_STATUS
+common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+#endif