mb/google/nissa/var/quandiso: Update initial files based on yavilla

Update files copied from yavilla
- fw_config setting
- GPIO setting
- Kconfig setting
- overridetree setting
- SPD memory parts
- variant setting

BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
flash bin file in DUT

Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 869 insertions, 8 deletions

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 7255e96717..f2ed8cab6b 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -171,6 +171,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x0 if BOARD_GOOGLE_GOTHRAX
 	default 0x0 if BOARD_GOOGLE_PIRRHA
 	default 0x1 if BOARD_GOOGLE_DOCHI
+	default 0x0 if BOARD_GOOGLE_QUANDISO
 
 config DRIVER_TPM_I2C_ADDR
 	hex
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 6ed217f5a5..97cfc9a09f 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -288,6 +288,14 @@ config BOARD_GOOGLE_PUJJO
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 
+config BOARD_GOOGLE_QUANDISO
+	bool "->  Quandiso"
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select HAVE_WWAN_POWER_SEQUENCE
+
 config BOARD_GOOGLE_REDRIX
 	bool "->  Redrix"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
@@ -430,10 +438,6 @@ config BOARD_GOOGLE_ZYDRON
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_RAPTORLAKE
 
-config BOARD_GOOGLE_QUANDISO
-	bool "->  Quandiso"
-	select BOARD_GOOGLE_BASEBOARD_NISSA
-
 config BOARD_GOOGLE_NOKRIS
 	bool "->  Nokris"
 	select BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/variants/quandiso/Makefile.inc b/src/mainboard/google/brya/variants/quandiso/Makefile.inc
new file mode 100644
index 0000000000..86ba20d3c3
--- /dev/null
+++ b/src/mainboard/google/brya/variants/quandiso/Makefile.inc
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/quandiso/fw_config.c b/src/mainboard/google/brya/variants/quandiso/fw_config.c
new file mode 100644
index 0000000000..0f08a43b83
--- /dev/null
+++ b/src/mainboard/google/brya/variants/quandiso/fw_config.c
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+
+static const struct pad_config lte_disable_pads[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
+	/* D6  : WWAN_EN */
+	PAD_NC(GPP_D6, NONE),
+	/* F12 : WWAN_RST_L */
+	PAD_NC(GPP_F12, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
+};
+
+static const struct pad_config wfc_disable_pads[] = {
+	/* D3  : WCAM_RST_L */
+	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D15 : EN_PP2800_WCAM_X */
+	PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
+	/* D16 : EN_PP1800_PP1200_WCAM_X */
+	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
+	/* H22 : WCAM_MCLK_R */
+	PAD_NC(GPP_H22, NONE),
+	/* R6 : DMIC_WCAM_CLK_R */
+	PAD_NC(GPP_R6, NONE),
+	/* R7 : DMIC_WCAM_DATA */
+	PAD_NC(GPP_R7, NONE),
+};
+
+static const struct pad_config emmc_disable_pads[] = {
+	/* I7  : EMMC_CMD */
+	PAD_NC(GPP_I7, NONE),
+	/* I8  : EMMC_D0 */
+	PAD_NC(GPP_I8, NONE),
+	/* I9  : EMMC_D1 */
+	PAD_NC(GPP_I9, NONE),
+	/* I10 : EMMC_D2 */
+	PAD_NC(GPP_I10, NONE),
+	/* I11 : EMMC_D3 */
+	PAD_NC(GPP_I11, NONE),
+	/* I12 : EMMC_D4 */
+	PAD_NC(GPP_I12, NONE),
+	/* I13 : EMMC_D5 */
+	PAD_NC(GPP_I13, NONE),
+	/* I14 : EMMC_D6 */
+	PAD_NC(GPP_I14, NONE),
+	/* I15 : EMMC_D7 */
+	PAD_NC(GPP_I15, NONE),
+	/* I16 : EMMC_RCLK */
+	PAD_NC(GPP_I16, NONE),
+	/* I17 : EMMC_CLK */
+	PAD_NC(GPP_I17, NONE),
+	/* I18 : EMMC_RST_L */
+	PAD_NC(GPP_I18, NONE),
+};
+
+static const struct pad_config stylus_disable_pads[] = {
+	/* F13 : SOC_PEN_DETECT_R_ODL */
+	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F15 : SOC_PEN_DETECT_ODL */
+	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
+};
+
+static const struct pad_config disable_wifi_pch_susclk[] = {
+	/* GPD8 ==> NC */
+	PAD_NC(GPD8, NONE),
+};
+
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
+{
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
+		printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
+		gpio_padbased_override(padbased_table, lte_disable_pads,
+				       ARRAY_SIZE(lte_disable_pads));
+	}
+	if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) {
+		printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
+		gpio_padbased_override(padbased_table, wfc_disable_pads,
+				       ARRAY_SIZE(wfc_disable_pads));
+	}
+	if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
+		printk(BIOS_INFO, "Disable eMMC GPIO pins.\n");
+		gpio_padbased_override(padbased_table, emmc_disable_pads,
+				       ARRAY_SIZE(emmc_disable_pads));
+	}
+	if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
+		printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
+		gpio_padbased_override(padbased_table, stylus_disable_pads,
+				       ARRAY_SIZE(stylus_disable_pads));
+	}
+	if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, SAR_ID_3))) {
+		printk(BIOS_INFO, "Disable PCH SUSCLK.\n");
+		gpio_padbased_override(padbased_table, disable_wifi_pch_susclk,
+					ARRAY_SIZE(disable_wifi_pch_susclk));
+	}
+}
diff --git a/src/mainboard/google/brya/variants/quandiso/gpio.c b/src/mainboard/google/brya/variants/quandiso/gpio.c
new file mode 100644
index 0000000000..e2f2aca857
--- /dev/null
+++ b/src/mainboard/google/brya/variants/quandiso/gpio.c
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* A18 : NC ==> HDMI_HPD_SRC */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+
+	/* D6  : WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D8  : SD_CLKREQ_ODL ==> NC  */
+	PAD_NC(GPP_D8, NONE),
+
+	/* F6  : CNV_PA_BLANKING ==> NC */
+	PAD_NC(GPP_F6, NONE),
+	/* F12 : WWAN_RST_ODL */
+	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+	/* F23 : V1P05EXT_CTRL ==> NC */
+	PAD_NC(GPP_F23, NONE),
+
+	/* H8  : CNV_MFUART2_RXD ==> NC */
+	PAD_NC(GPP_H8, NONE),
+	/* H9  : CNV_MFUART2_TXD ==> NC */
+	PAD_NC(GPP_H9, NONE),
+	/* H12 : SD_PERST_L ==> NC */
+	PAD_NC(GPP_H12, NONE),
+	/* H13 : EN_PP3300_SD_X ==> NC */
+	PAD_NC(GPP_H13, NONE),
+	/* H15 : HDMI_SRC_SCL */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H17 : HDMI_SRC_SDA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H19 : SRCCLKREQ4# ==> NC */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* D6  : WWAN_EN */
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
+	PAD_CFG_GPO(GPP_B11, 1, DEEP),
+	/* F12 : WWAN_RST_ODL */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* Enable touchscreen, hold in reset */
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
+	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H20, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/quandiso/include/variant/gpio.h b/src/mainboard/google/brya/variants/quandiso/include/variant/gpio.h
index c4fe342621..c96b01fc15 100644
--- a/src/mainboard/google/brya/variants/quandiso/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/quandiso/include/variant/gpio.h
@@ -5,4 +5,8 @@
 
 #include <baseboard/gpio.h>
 
+#define WWAN_FCPO	GPP_D6
+#define WWAN_RST	GPP_F12
+#define T2_OFF_MS	20
+
 #endif
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.inc b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.inc
index eace2e443e..0aa403852a 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/quandiso/memory/Makefile.inc
@@ -1,5 +1,13 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/quandiso/memory src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
 
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 1(0b0001)  Parts = MT62F1G32D4DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 3(0b0011)  Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 4(0b0100)  Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 5(0b0101)  Parts = H58G66AK6BX070
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex      # ID = 6(0b0110)  Parts = K3KL6L60GM-MGCT
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
index fa247902ee..576ef70d35 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt
@@ -1 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen ADL lp5
+src/mainboard/google/brya/variants/quandiso/memory
+src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
+
 DRAM Part Name                 ID to assign
+MT62F512M32D2DR-031 WT:B       0 (0000)
+MT62F1G32D4DR-031 WT:B         1 (0001)
+H9JCNNNBK3MLYR-N6E             0 (0000)
+H58G56AK6BX069                 2 (0010)
+K3LKBKB0BM-MGCP                2 (0010)
+H58G56BK7BX068                 3 (0011)
+MT62F1G32D2DS-026 WT:B         3 (0011)
+K3KL8L80CM-MGCT                3 (0011)
+H58G66BK7BX067                 4 (0100)
+MT62F2G32D4DS-026 WT:B         4 (0100)
+K3KL9L90CM-MGCT                4 (0100)
+H58G66AK6BX070                 5 (0101)
+K3KL6L60GM-MGCT                6 (0110)
diff --git a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
index 96211370d9..9e8d0c979c 100644
--- a/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt
@@ -9,3 +9,16 @@
 # See util/spd_tools/README.md for more details and instructions.
 
 # Part Name
+MT62F512M32D2DR-031 WT:B
+MT62F1G32D4DR-031 WT:B
+H9JCNNNBK3MLYR-N6E
+H58G56AK6BX069
+K3LKBKB0BM-MGCP
+H58G56BK7BX068
+MT62F1G32D2DS-026 WT:B
+K3KL8L80CM-MGCT
+H58G66BK7BX067
+MT62F2G32D4DS-026 WT:B
+K3KL9L90CM-MGCT
+H58G66AK6BX070
+K3KL6L60GM-MGCT
diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb
index 4f2c04a57a..6d2b47f918 100644
--- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb
+++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb
@@ -1,6 +1,572 @@
+fw_config
+	field DB_USB 0 1
+		option DB_NONE			0
+		option DB_1C_1A			1
+		option DB_1C			2
+		option DB_1C_LTE		3
+	end
+	field WIFI_SAR_ID 2 3
+		option SAR_ID_0			0
+		option SAR_ID_1			1
+		option SAR_ID_2			2
+		option SAR_ID_3			3
+	end
+	field STYLUS 9
+		option STYLUS_ABSENT		0
+		option STYLUS_PRESENT		1
+	end
+	field SD_CARD 10
+		option SD_PRESENT		0
+		option SD_ABSENT		1
+	end
+	field WFC 11
+		option WFC_ABSENT		0
+		option WFC_MIPI_OVTI8856	1
+	end
+	field MB_HDMI 12
+		option HDMI_ABSENT		0
+		option HDMI_PRESENT		1
+	end
+	field MB_USB 15
+		option MB_1C			0
+		option MB_1C_2A			1
+	end
+	field WIFI_SAR_ID2 16 19
+		option INTEL_YAVILLA_LTE	0
+		option INTEL_YAVILLA_WIFI	1
+		option INTEL_YAVILLY_LTE	2
+		option INTEL_YAVILLY_WIFI	3
+		option INTEL_YAVIJO_LTE		4
+		option INTEL_YAVIJO_WIFI	5
+		option UNUSED			15
+	end
+end
+
 chip soc/intel/alderlake
+	register "sagv" = "SaGv_Enabled"
+
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-42.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-42.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-42.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C272828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-42.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C171733"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-42.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10024"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-42.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414"
+
+	# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
+	# Bit 2 - C1 has a redriver which does SBU muxing.
+	# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
+	register "tcss_aux_ori" = "1"
+
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 WWAN
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN
+
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN
+
+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | TPM. Early init is        |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | WCAM                      |
+	#| I2C3              | Audio                     |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST_PLUS,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST_PLUS,
+				.scl_lcnt = 56,
+				.scl_hcnt = 30,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 30,
+			}
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 7,
+			}
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 158,
+				.scl_hcnt = 79,
+				.sda_hold = 40,
+			}
+		},
+	}"
+
+	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""CPU""
+				register "options.tsr[1].desc" = ""5V Regulator""
+				register "options.tsr[2].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 6000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on end
+			end
+		end
+		device ref ipu on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "1"
+				register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
+				register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
+				register "cio2_prt[0]" = "1"
+				device generic 0 on end
+			end
+			probe WFC WFC_MIPI_OVTI8856
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "detect" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "reset_delay_ms" = "20"
+				register "reset_off_delay_ms" = "2"
+				register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "stop_delay_ms" = "280"
+				register "stop_off_delay_ms" = "2"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "1"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN2513""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.detect" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+				register "generic.reset_delay_ms" = "50"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 40 on end
+			end
+			chip drivers/generic/gpio_keys
+				register "name" = ""PENH""
+				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
+				register "key.wake_gpe" = "GPE0_DW2_15"
+				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
+				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+				register "key.dev_name" = ""EJCT""
+				register "key.linux_code" = "SW_PEN_INSERTED"
+				register "key.linux_input_type" = "EV_SW"
+				register "key.label" = ""pen_eject""
+				device generic 0 on
+					probe STYLUS STYLUS_PRESENT
+				end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI8856""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 8856 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "1"
+				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
+
+				register "ssdb.lanes_used" = "4"
+				register "ssdb.link_used" = "1"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "2"
+				register "link_freq[0]" = "360000000"
+				register "link_freq[1]" = "180000000"
+				register "remote_name" = ""IPU0""
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
+				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
+				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3"   # WCAM_RST_L
+
+				#_ON
+				register "on_seq.ops_cnt" = "5"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "4"
+				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+				device i2c 36 on
+					probe WFC WFC_MIPI_OVTI8856
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW AF DAC""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				device i2c 0C on
+					probe WFC WFC_MIPI_OVTI8856
+				end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "1"
+				register "acpi_name" = ""NVM0""
+				register "chip_name" = ""GT24C08""
+				register "device_type" = "INTEL_ACPI_CAMERA_NVM"
 
-        device domain 0 on
-        end
+				register "nvm_size" = "0x400"
+				register "nvm_pagesize" = "1"
+				register "nvm_readonly" = "1"
+				register "nvm_width" = "0x08"
+				register "nvm_compat" = ""atmel,24c08""
 
+				device i2c 50 on
+					probe WFC WFC_MIPI_OVTI8856
+				end
+			end
+		end
+		device ref i2c3 on
+			chip drivers/i2c/generic
+				register "hid" = ""RTL5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "wake" = "GPE0_DW2_14"
+				register "detect" = "1"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA0000""
+				register "generic.cid" = ""ACPI0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+				register "generic.wake" = "GPE0_DW2_14"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "sdmode_delay" = "5"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp4 on
+			# PCIe 4 WLAN
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on end
+			end
+		end
+		device ref pcie_rp7 off end #PCIE7 no SD card
+		device ref emmc on end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref ufs on end
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C1 (DB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+                                                register "use_custom_pld" = "true"
+                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (MLB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on
+							probe DB_USB DB_1C_LTE
+						end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 UFC""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVi Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (MLB)""
+						register "type" = "UPC_TYPE_USB3_A"
+                                                register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+                                                register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port3 on
+							probe DB_USB DB_1C_LTE
+						end
+					end
+				end
+			end
+		end
+	end
 end
diff --git a/src/mainboard/google/brya/variants/quandiso/variant.c b/src/mainboard/google/brya/variants/quandiso/variant.c
new file mode 100644
index 0000000000..9140eb043f
--- /dev/null
+++ b/src/mainboard/google/brya/variants/quandiso/variant.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <device/device.h>
+#include <fw_config.h>
+#include <sar.h>
+
+void variant_devtree_update(void)
+{
+	struct device *emmc = DEV_PTR(emmc);
+	struct device *ufs = DEV_PTR(ufs);
+	struct device *ish = DEV_PTR(ish);
+
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_INFO, "fw_config unprovisioned so enable all storage devices\n");
+		return;
+	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
+		printk(BIOS_INFO, "eMMC disabled by fw_config\n");
+		emmc->enabled = 0;
+	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+		printk(BIOS_INFO, "UFS disabled by fw_config\n");
+		ufs->enabled = 0;
+		ish->enabled = 0;
+	}
+}
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID2));
+}