diff options
| author | Shon Wang <shon.wang@quanta.corp-partner.google.com> | 2024-06-04 20:19:09 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-07 18:35:36 +0000 |
| commit | f857d30787fab6a35e952f6e236cf32e50240261 (patch) | |
| tree | 8e79d9ae44e603595da230ddb0b247de68d731b7 /src/mainboard | |
| parent | 6e755cef04632b92d8e5a24f507613fc7bea346d (diff) | |
mb/google/brask/var/bujia: fix type-c USB2 problem
Enable type-c port 0 USB2 function.
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I0d7adc329a8c26941957d7a7472a5166b07bda5b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82903
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/bujia/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index f3589b970e..252d82f8a5 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -29,6 +29,7 @@ chip soc/intel/alderlake }, }" + register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface |