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authorDaolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>2021-09-15 13:01:55 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-10-02 11:48:34 +0000
commitf4b71734b266b5cf276e7bd3b0de45553a0728bd (patch)
tree85e45203fb6a32dc86f527c74ef9c9f4ae9d369e /src/mainboard
parent38abbdab71e6bf275c9c49748f1830576ddb2f22 (diff)
soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed
1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/cherry/bootblock.c2
-rw-r--r--src/mainboard/google/cherry/mainboard.c4
-rw-r--r--src/mainboard/google/cherry/romstage.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c
index dca2f1383a..c506cafc27 100644
--- a/src/mainboard/google/cherry/bootblock.c
+++ b/src/mainboard/google/cherry/bootblock.c
@@ -43,7 +43,7 @@ static void usb3_hub_reset(void)
void bootblock_mainboard_init(void)
{
- mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
+ mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
nor_set_gpio_pinmux();
setup_chromeos_gpios();
diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c
index 7b9ba658d1..a09705019e 100644
--- a/src/mainboard/google/cherry/mainboard.c
+++ b/src/mainboard/google/cherry/mainboard.c
@@ -131,7 +131,7 @@ static void configure_sdcard(void)
MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE,
MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE);
- mtk_i2c_bus_init(I2C7);
+ mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST);
if (CONFIG(BOARD_GOOGLE_CHERRY))
mt6360_init(I2C7);
@@ -205,7 +205,7 @@ static void mainboard_init(struct device *dev)
/* for audio usage */
if (CONFIG(CHERRY_USE_RT1011))
- mtk_i2c_bus_init(I2C2);
+ mtk_i2c_bus_init(I2C2, I2C_SPEED_FAST);
if (dpm_init())
printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");
diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c
index 71291c24a3..f375867c28 100644
--- a/src/mainboard/google/cherry/romstage.c
+++ b/src/mainboard/google/cherry/romstage.c
@@ -28,7 +28,7 @@ void platform_romstage_main(void)
mt6359p_init();
mt6315_init();
raise_little_cpu_freq();
- mtk_i2c_bus_init(I2C7);
+ mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST);
if (CONFIG(BOARD_GOOGLE_CHERRY))
mt6360_init(I2C7);
clk_buf_init();