mb/dell: Add Latitude E6430 (Ivy Bridge)

Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU was
not tested. This is based on the autoport output with some manual fixes.
The VBT was obtained using `intelvbttool --inlegacy --outvbt data.vbt`
while running version A24 (latest version) of the vendor firmware.

The flash is 8MiB + 4MiB, and can be easily accessed by removing the
keyboard. It can also be internally flashed by sending a command to the
EC, which causes the EC to pull the FDO pin low and the firmware to skip
setting up any chipset based write protections [1]. The EC is the SMSC
MEC5055, which seems to be compatible with the existing MEC5035 code.

Working:
- Libgfxinit
- USB EHCI debug (left side usb port is HCD index 2, middle port on the
  right side is HCD index 1) with the CH347
- Keyboard
- Touchpad/trackpoint
- ExpressCard (tested with USB 3.0 card)
- Audio
- Ethernet
- SD card reader
- mPCIe WiFi
- SeaBIOS 1.16.3
- edk2 (MrChromebox's fork, uefipayload_202309)
- Internal flashing using dell-flash-unlock

Not working:
- S3 suspend: Possibly EC related, DRAM power is getting cut when
  entering S3
- Physical wireless switch: this triggers an SMI handler in the vendor
  firmware which sends commands to the EC to enable/disable wireless
  devices, and has not been reimplemented
- Battery reporting: needs ACPI code for the EC
- Brightness hotkeys: probably EC related
- The system reports that the power button was pressed and shuts down
  when the CPU hits around 86 degrees Celsius, before the CPU can
  thermal throttle. Likely EC and possibly PECI related.
- Integrated keyboard with upstream GRUB 2.12 payload: Upstream GRUB
  initializes the 8042 PS/2 controller in a way that is incompatible
  with how the EC firmware emulates it. GRUB tries to initialize the
  controller with scan code set 2 without translation, but the EC only
  ever returns set 1 scan codes to the system and thus is only works as
  an untranslated set 1 keyboard or a translated set 2 keyboard,
  regardless of commands to set the scan code. A USB keyboard works
  fine.

Unknown/untested:
- Dock
- eSATA
- TPM
- dGPU on non-UMA model
- Bluetooth module (not included on my system)

[1] https://gitlab.com/nic3-14159/dell-flash-unlock

Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77444
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

18 files changed, 584 insertions, 0 deletions

diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
new file mode 100644
index 0000000000..be9ac37845
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -0,0 +1,49 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	def_bool n
+	select EC_ACPI
+	select EC_DELL_MEC5035
+	select GFX_GMA_PANEL_1_ON_LVDS
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SYSTEM_TYPE_LAPTOP
+	select USE_NATIVE_RAMINIT
+
+config BOARD_DELL_LATITUDE_E6430
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_12288
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_C216
+
+if BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+
+config DRAM_RESET_GATE_GPIO
+	default 60
+
+config MAINBOARD_DIR
+	default "dell/snb_ivb_latitude"
+
+config MAINBOARD_PART_NUMBER
+	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config USBDEBUG_HCD_INDEX
+	default 2
+
+config VARIANT_DIR
+	default "e6430" if BOARD_DELL_LATITUDE_E6430
+
+config VGA_BIOS_ID
+	default "8086,0166"
+
+endif
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
new file mode 100644
index 0000000000..183252630a
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_LATITUDE_E6430
+	bool "Latitude E6430"
diff --git a/src/mainboard/dell/snb_ivb_latitude/Makefile.mk b/src/mainboard/dell/snb_ivb_latitude/Makefile.mk
new file mode 100644
index 0000000000..299fbb9bad
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+
+romstage-y += variants/$(VARIANT_DIR)/early_init.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
diff --git a/src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl b/src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 0)
+	Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl b/src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	/* FIXME: EC support  */
+	Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+	/* FIXME: EC support  */
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl b/src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/snb_ivb_latitude/board_info.txt b/src/mainboard/dell/snb_ivb_latitude/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
new file mode 100644
index 0000000000..2a5b30f2b7
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Normal
diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.layout b/src/mainboard/dell/snb_ivb_latitude/cmos.layout
new file mode 100644
index 0000000000..9561c4e679
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.layout
@@ -0,0 +1,83 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+#400	8	r	0	reserved for century byte
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+409	2	e	7	power_on_after_fail
+411     1       e       9       sata_mode
+
+# coreboot config options: EC
+412	1	e	1	bluetooth
+413	1	e	1	wwan
+414	1	e	1	wlan
+
+# coreboot config options: ME
+424	1	e	14	me_state
+425	2	h	0	me_state_prev
+
+# coreboot config options: northbridge
+432	3	e	11	gfx_uma_size
+
+# SandyBridge MRC Scrambler Seed values
+896	32	r	0	mrc_scrambler_seed
+928	32	r	0	mrc_scrambler_seed_s3
+960	16	r	0	mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+2	0	Enable
+2	1	Disable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+9	0	AHCI
+9	1	Compatible
+11	0	32M
+11	1	64M
+11	2	96M
+11	3	128M
+11	4	160M
+11	5	192M
+11	6	224M
+14	0	Normal
+14	1	Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/snb_ivb_latitude/devicetree.cb b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb
new file mode 100644
index 0000000000..f00922b8c7
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb
@@ -0,0 +1,56 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+	device domain 0x0 on
+		device ref igd on
+			register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+			register "gpu_dp_b_hotplug" = "4"
+			register "gpu_dp_c_hotplug" = "4"
+			register "gpu_dp_d_hotplug" = "4"
+			register "gpu_panel_port_select" = "0"
+			register "gpu_panel_power_backlight_off_delay" = "2300"
+			register "gpu_panel_power_backlight_on_delay" = "2300"
+			register "gpu_panel_power_cycle_delay" = "6"
+			register "gpu_panel_power_down_delay" = "400"
+			register "gpu_panel_power_up_delay" = "400"
+		end
+
+		chip southbridge/intel/bd82x6x # Intel 6/7 Series PCH
+			register "docking_supported" = "1"
+
+			register "gpi0_routing" = "2"
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+			register "pcie_port_coalesce" = "1"
+
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+
+			device ref gbe		on end
+			device ref ehci2	on end
+			device ref hda		on end
+			device ref pcie_rp1	on end # WWAN Slot
+			device ref pcie_rp2	on end # SLAN Slot
+			device ref pcie_rp3	on end # ExpressCard
+			device ref pcie_rp4	on end # E-Module (optical bay)
+			device ref pcie_rp5	on end # Extra Half Mini PCIe slot
+			device ref pcie_rp6	on end # SD/MMC Card Reader
+			device ref ehci1	on end
+			device ref lpc		on
+				register "gen1_dec" = "0x007c0681"
+				register "gen2_dec" = "0x005c0921"
+				register "gen3_dec" = "0x003c07e1"
+				register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+
+				chip ec/dell/mec5035
+					device pnp ff.0 on end
+				end
+			end
+			device ref sata1	on
+				register "sata_interface_speed_support" = "0x3"
+				register "sata_port_map" = "0x33"
+			end
+		end
+	end
+end
diff --git a/src/mainboard/dell/snb_ivb_latitude/dsdt.asl b/src/mainboard/dell/snb_ivb_latitude/dsdt.asl
new file mode 100644
index 0000000000..9a7d54b963
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018	/* OEM revision */
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads b/src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads
new file mode 100644
index 0000000000..ea6dfb06ed
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads
@@ -0,0 +1,22 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (
+      HDMI1, -- mainboard HDMI
+      HDMI2, -- dock DVI
+      HDMI3, -- dock DVI
+      DP2, -- dock DP
+      DP3, -- dock DP
+      Analog, -- mainboard/dock VGA (muxed)
+      LVDS,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/snb_ivb_latitude/mainboard.c b/src/mainboard/dell/snb_ivb_latitude/mainboard.c
new file mode 100644
index 0000000000..1d13a8459b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/mainboard.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+	/* FIXME: fix these values. */
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+					GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+	pc_keyboard_init(NO_AUX_DEVICE);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt
new file mode 100644
index 0000000000..ec55884811
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c
new file mode 100644
index 0000000000..b4fd22d3d5
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 },
+	{ 1, 1, 0 },
+	{ 1, 1, 1 },
+	{ 1, 1, 1 },
+	{ 1, 0, 2 },
+	{ 1, 1, 2 },
+	{ 1, 1, 3 },
+	{ 1, 1, 3 },
+	{ 1, 1, 4 },
+	{ 1, 1, 4 },
+	{ 1, 1, 5 },
+	{ 1, 1, 5 },
+	{ 1, 2, 6 },
+	{ 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c
new file mode 100644
index 0000000000..f069813b67
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
+	0x10280534,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10280534),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb
new file mode 100644
index 0000000000..55df5eba1d
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb
@@ -0,0 +1,20 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x0534 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00001312"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			device ref xhci on
+				register "superspeed_capable_ports" = "0x0000000f"
+				register "xhci_overcurrent_mapping" = "0x00000c03"
+				register "xhci_switchable_ports" = "0x0000000f"
+			end
+		end
+	end
+end