PIT: memory setup

Tested and working. Gets us to ramstage.

Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 98 insertions, 457 deletions

diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig
index 8aed0a057d..0dc013b231 100644
--- a/src/mainboard/google/pit/Kconfig
+++ b/src/mainboard/google/pit/Kconfig
@@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select DRIVER_TI_TPS65090
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT
+	select HAVE_INIT_TIMER
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c
index 68c2bd6145..74f3e6eb9c 100644
--- a/src/mainboard/google/pit/memory.c
+++ b/src/mainboard/google/pit/memory.c
@@ -23,147 +23,21 @@
 #include <console/console.h>
 
 #include <cpu/samsung/exynos5420/gpio.h>
-#include <cpu/samsung/exynos5420/setup.h>
 #include <cpu/samsung/exynos5420/dmc.h>
+#include <cpu/samsung/exynos5420/setup.h>
 #include <cpu/samsung/exynos5420/clk.h>
 
-const struct mem_timings mem_timings[] = {
-	{
-		.mem_manuf = MEM_MANUF_ELPIDA,
-		.mem_type = DDR_MODE_DDR3,
-		.frequency_mhz = 800,
-		.mpll_mdiv = 0x64,
-		.mpll_pdiv = 0x3,
-		.mpll_sdiv = 0x0,
-		.cpll_mdiv = 0xde,
-		.cpll_pdiv = 0x4,
-		.cpll_sdiv = 0x2,
-		.gpll_mdiv = 0x215,
-		.gpll_pdiv = 0xc,
-		.gpll_sdiv = 0x1,
-		.epll_mdiv = 0x60,
-		.epll_pdiv = 0x3,
-		.epll_sdiv = 0x3,
-		.vpll_mdiv = 0x96,
-		.vpll_pdiv = 0x3,
-		.vpll_sdiv = 0x2,
-
-		.bpll_mdiv = 0x64,
-		.bpll_pdiv = 0x3,
-		.bpll_sdiv = 0x0,
-		.use_bpll = 0,
-		.pclk_cdrex_ratio = 0x5,
-		.direct_cmd_msr = {
-			0x00020018, 0x00030000, 0x00010042, 0x00000d70
-		},
-		.timing_ref = 0x000000bb,
-		.timing_row = 0x8c36660f,
-		.timing_data = 0x3630580b,
-		.timing_power = 0x41000a44,
-		.phy0_dqs = 0x08080808,
-		.phy1_dqs = 0x08080808,
-		.phy0_dq = 0x08080808,
-		.phy1_dq = 0x08080808,
-		.phy0_tFS = 0x4,
-		.phy1_tFS = 0x4,
-		.phy0_pulld_dqs = 0xf,
-		.phy1_pulld_dqs = 0xf,
-
-		.lpddr3_ctrl_phy_reset = 0x1,
-		.ctrl_start_point = 0x10,
-		.ctrl_inc = 0x10,
-		.ctrl_start = 0x1,
-		.ctrl_dll_on = 0x1,
-		.ctrl_ref = 0x8,
-
-		.ctrl_force = 0x1a,
-		.ctrl_rdlat = 0x0b,
-		.ctrl_bstlen = 0x08,
-
-		.fp_resync = 0x8,
-		.iv_size = 0x7,
-		.dfi_init_start = 1,
-		.aref_en = 1,
-
-		.rd_fetch = 0x3,
-
-		.zq_mode_dds = 0x7,
-		.zq_mode_term = 0x1,
-		.zq_mode_noterm = 0,
-
-		/*
-		* Dynamic Clock: Always Running
-		* Memory Burst length: 8
-		* Number of chips: 1
-		* Memory Bus width: 32 bit
-		* Memory Type: DDR3
-		* Additional Latancy for PLL: 0 Cycle
-		*/
-		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
-			DMC_MEMCONTROL_DPWRDN_DISABLE |
-			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
-			DMC_MEMCONTROL_TP_DISABLE |
-			DMC_MEMCONTROL_DSREF_ENABLE |
-			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
-			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
-			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
-			DMC_MEMCONTROL_NUM_CHIP_1 |
-			DMC_MEMCONTROL_BL_8 |
-			DMC_MEMCONTROL_PZQ_DISABLE |
-			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
-			DMC_MEMCONFIGx_CHIP_BANK_8,
-		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
-		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
-		.prechconfig_tp_cnt = 0xff,
-		.dpwrdn_cyc = 0xff,
-		.dsref_cyc = 0xffff,
-		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
-			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
-			DMC_CONCONTROL_RD_FETCH_DISABLE |
-			DMC_CONCONTROL_EMPTY_DISABLE |
-			DMC_CONCONTROL_AREF_EN_DISABLE |
-			DMC_CONCONTROL_IO_PD_CON_DISABLE,
-		.dmc_channels = 2,
-		.chips_per_channel = 2,
-		.chips_to_configure = 1,
-		.send_zq_init = 1,
-		.impedance = IMP_OUTPUT_DRV_30_OHM,
-		.gate_leveling_enable = 0,
-	}, {
+const struct mem_timings mem_timings = {
 		.mem_manuf = MEM_MANUF_SAMSUNG,
 		.mem_type = DDR_MODE_DDR3,
 		.frequency_mhz = 800,
-		.mpll_mdiv = 0x64,
-		.mpll_pdiv = 0x3,
-		.mpll_sdiv = 0x0,
-		.cpll_mdiv = 0xde,
-		.cpll_pdiv = 0x4,
-		.cpll_sdiv = 0x2,
-		.gpll_mdiv = 0x215,
-		.gpll_pdiv = 0xc,
-		.gpll_sdiv = 0x1,
-		.epll_mdiv = 0x60,
-		.epll_pdiv = 0x3,
-		.epll_sdiv = 0x3,
-		.vpll_mdiv = 0x96,
-		.vpll_pdiv = 0x3,
-		.vpll_sdiv = 0x2,
-
-		.bpll_mdiv = 0x64,
-		.bpll_pdiv = 0x3,
-		.bpll_sdiv = 0x0,
-		.use_bpll = 0,
-		.pclk_cdrex_ratio = 0x5,
 		.direct_cmd_msr = {
-			0x00020018, 0x00030000, 0x00010000, 0x00000d70
+			0x00020018, 0x00030000, 0x00010002, 0x00000d70
 		},
 		.timing_ref = 0x000000bb,
-		.timing_row = 0x8c36660f,
+		.timing_row = 0x6836650f,
 		.timing_data = 0x3630580b,
-		.timing_power = 0x41000a44,
+		.timing_power = 0x41000a26,
 		.phy0_dqs = 0x08080808,
 		.phy1_dqs = 0x08080808,
 		.phy0_dq = 0x08080808,
@@ -191,7 +65,7 @@ const struct mem_timings mem_timings[] = {
 
 		.rd_fetch = 0x3,
 
-		.zq_mode_dds = 0x5,
+		.zq_mode_dds = 0x6,
 		.zq_mode_term = 0x1,
 		.zq_mode_noterm = 1,
 
@@ -207,20 +81,18 @@ const struct mem_timings mem_timings[] = {
 			DMC_MEMCONTROL_DPWRDN_DISABLE |
 			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
 			DMC_MEMCONTROL_TP_DISABLE |
-			DMC_MEMCONTROL_DSREF_ENABLE |
+			DMC_MEMCONTROL_DSREF_DISABLE |
 			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
 			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
 			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
-			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_NUM_CHIP_2 |
 			DMC_MEMCONTROL_BL_8 |
 			DMC_MEMCONTROL_PZQ_DISABLE |
 			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
+		.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
 			DMC_MEMCONFIGx_CHIP_COL_10 |
 			DMC_MEMCONFIGx_CHIP_ROW_15 |
 			DMC_MEMCONFIGx_CHIP_BANK_8,
-		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
-		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
 		.prechconfig_tp_cnt = 0xff,
 		.dpwrdn_cyc = 0xff,
 		.dsref_cyc = 0xffff,
@@ -230,316 +102,9 @@ const struct mem_timings mem_timings[] = {
 			DMC_CONCONTROL_EMPTY_DISABLE |
 			DMC_CONCONTROL_AREF_EN_DISABLE |
 			DMC_CONCONTROL_IO_PD_CON_DISABLE,
-		.dmc_channels = 2,
+		.dmc_channels = 1,
 		.chips_per_channel = 2,
-		.chips_to_configure = 1,
+		.chips_to_configure = 2,
 		.send_zq_init = 1,
-		.impedance = IMP_OUTPUT_DRV_40_OHM,
 		.gate_leveling_enable = 1,
-	},
-	{
-		.mem_manuf = MEM_MANUF_ELPIDA,
-		.mem_type = DDR_MODE_DDR3,
-		.frequency_mhz = 780,
-		.mpll_mdiv = 0x64,
-		.mpll_pdiv = 0x3,
-		.mpll_sdiv = 0x0,
-		.cpll_mdiv = 0xde,
-		.cpll_pdiv = 0x4,
-		.cpll_sdiv = 0x2,
-		.gpll_mdiv = 0x215,
-		.gpll_pdiv = 0xc,
-		.gpll_sdiv = 0x1,
-		.epll_mdiv = 0x60,
-		.epll_pdiv = 0x3,
-		.epll_sdiv = 0x3,
-		.vpll_mdiv = 0x96,
-		.vpll_pdiv = 0x3,
-		.vpll_sdiv = 0x2,
-
-		.bpll_mdiv = 0x82,
-		.bpll_pdiv = 0x4,
-		.bpll_sdiv = 0x0,
-		.use_bpll = 1,
-		.pclk_cdrex_ratio = 0x5,
-		.direct_cmd_msr = {
-			0x00020018, 0x00030000, 0x00010042, 0x00000d70
-		},
-		.timing_ref = 0x000000bb,
-		.timing_row = 0x8c36660f,
-		.timing_data = 0x3630580b,
-		.timing_power = 0x41000a44,
-		.phy0_dqs = 0x08080808,
-		.phy1_dqs = 0x08080808,
-		.phy0_dq = 0x08080808,
-		.phy1_dq = 0x08080808,
-		.phy0_tFS = 0x4,
-		.phy1_tFS = 0x4,
-		.phy0_pulld_dqs = 0xf,
-		.phy1_pulld_dqs = 0xf,
-
-		.lpddr3_ctrl_phy_reset = 0x1,
-		.ctrl_start_point = 0x10,
-		.ctrl_inc = 0x10,
-		.ctrl_start = 0x1,
-		.ctrl_dll_on = 0x1,
-		.ctrl_ref = 0x8,
-
-		.ctrl_force = 0x1a,
-		.ctrl_rdlat = 0x0b,
-		.ctrl_bstlen = 0x08,
-
-		.fp_resync = 0x8,
-		.iv_size = 0x7,
-		.dfi_init_start = 1,
-		.aref_en = 1,
-
-		.rd_fetch = 0x3,
-
-		.zq_mode_dds = 0x7,
-		.zq_mode_term = 0x1,
-		.zq_mode_noterm = 0,
-
-		/*
-		* Dynamic Clock: Always Running
-		* Memory Burst length: 8
-		* Number of chips: 1
-		* Memory Bus width: 32 bit
-		* Memory Type: DDR3
-		* Additional Latancy for PLL: 0 Cycle
-		*/
-		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
-			DMC_MEMCONTROL_DPWRDN_DISABLE |
-			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
-			DMC_MEMCONTROL_TP_DISABLE |
-			DMC_MEMCONTROL_DSREF_ENABLE |
-			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
-			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
-			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
-			DMC_MEMCONTROL_NUM_CHIP_1 |
-			DMC_MEMCONTROL_BL_8 |
-			DMC_MEMCONTROL_PZQ_DISABLE |
-			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
-			DMC_MEMCONFIGx_CHIP_BANK_8,
-		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
-		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
-		.prechconfig_tp_cnt = 0xff,
-		.dpwrdn_cyc = 0xff,
-		.dsref_cyc = 0xffff,
-		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
-			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
-			DMC_CONCONTROL_RD_FETCH_DISABLE |
-			DMC_CONCONTROL_EMPTY_DISABLE |
-			DMC_CONCONTROL_AREF_EN_DISABLE |
-			DMC_CONCONTROL_IO_PD_CON_DISABLE,
-		.dmc_channels = 2,
-		.chips_per_channel = 2,
-		.chips_to_configure = 1,
-		.send_zq_init = 1,
-		.impedance = IMP_OUTPUT_DRV_30_OHM,
-		.gate_leveling_enable = 0,
-	}, {
-		.mem_manuf = MEM_MANUF_SAMSUNG,
-		.mem_type = DDR_MODE_DDR3,
-		.frequency_mhz = 780,
-		.mpll_mdiv = 0x64,
-		.mpll_pdiv = 0x3,
-		.mpll_sdiv = 0x0,
-		.cpll_mdiv = 0xde,
-		.cpll_pdiv = 0x4,
-		.cpll_sdiv = 0x2,
-		.gpll_mdiv = 0x215,
-		.gpll_pdiv = 0xc,
-		.gpll_sdiv = 0x1,
-		.epll_mdiv = 0x60,
-		.epll_pdiv = 0x3,
-		.epll_sdiv = 0x3,
-		.vpll_mdiv = 0x96,
-		.vpll_pdiv = 0x3,
-		.vpll_sdiv = 0x2,
-
-		.bpll_mdiv = 0x82,
-		.bpll_pdiv = 0x4,
-		.bpll_sdiv = 0x0,
-		.use_bpll = 1,
-		.pclk_cdrex_ratio = 0x5,
-		.direct_cmd_msr = {
-			0x00020018, 0x00030000, 0x00010000, 0x00000d70
-		},
-		.timing_ref = 0x000000bb,
-		.timing_row = 0x8c36660f,
-		.timing_data = 0x3630580b,
-		.timing_power = 0x41000a44,
-		.phy0_dqs = 0x08080808,
-		.phy1_dqs = 0x08080808,
-		.phy0_dq = 0x08080808,
-		.phy1_dq = 0x08080808,
-		.phy0_tFS = 0x8,
-		.phy1_tFS = 0x8,
-		.phy0_pulld_dqs = 0xf,
-		.phy1_pulld_dqs = 0xf,
-
-		.lpddr3_ctrl_phy_reset = 0x1,
-		.ctrl_start_point = 0x10,
-		.ctrl_inc = 0x10,
-		.ctrl_start = 0x1,
-		.ctrl_dll_on = 0x1,
-		.ctrl_ref = 0x8,
-
-		.ctrl_force = 0x1a,
-		.ctrl_rdlat = 0x0b,
-		.ctrl_bstlen = 0x08,
-
-		.fp_resync = 0x8,
-		.iv_size = 0x7,
-		.dfi_init_start = 1,
-		.aref_en = 1,
-
-		.rd_fetch = 0x3,
-
-		.zq_mode_dds = 0x5,
-		.zq_mode_term = 0x1,
-		.zq_mode_noterm = 1,
-
-		/*
-		* Dynamic Clock: Always Running
-		* Memory Burst length: 8
-		* Number of chips: 1
-		* Memory Bus width: 32 bit
-		* Memory Type: DDR3
-		* Additional Latancy for PLL: 0 Cycle
-		*/
-		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
-			DMC_MEMCONTROL_DPWRDN_DISABLE |
-			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
-			DMC_MEMCONTROL_TP_DISABLE |
-			DMC_MEMCONTROL_DSREF_ENABLE |
-			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
-			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
-			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
-			DMC_MEMCONTROL_NUM_CHIP_1 |
-			DMC_MEMCONTROL_BL_8 |
-			DMC_MEMCONTROL_PZQ_DISABLE |
-			DMC_MEMCONTROL_MRR_BYTE_7_0,
-		.memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
-			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
-			DMC_MEMCONFIGx_CHIP_BANK_8,
-		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
-		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
-		.prechconfig_tp_cnt = 0xff,
-		.dpwrdn_cyc = 0xff,
-		.dsref_cyc = 0xffff,
-		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
-			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
-			DMC_CONCONTROL_RD_FETCH_DISABLE |
-			DMC_CONCONTROL_EMPTY_DISABLE |
-			DMC_CONCONTROL_AREF_EN_DISABLE |
-			DMC_CONCONTROL_IO_PD_CON_DISABLE,
-		.dmc_channels = 2,
-		.chips_per_channel = 2,
-		.chips_to_configure = 1,
-		.send_zq_init = 1,
-		.impedance = IMP_OUTPUT_DRV_40_OHM,
-		.gate_leveling_enable = 1,
-	}
 };
-
-#define BOARD_ID0_GPIO	88	/* GPD0, pin 0 */
-#define BOARD_ID1_GPIO	89	/* GPD0, pin 1 */
-
-enum board_config {
-	PIT_CONFIG_UNKNOWN = -1,
-	PIT_CONFIG_SAMSUNG_EVT,
-	PIT_CONFIG_ELPIDA_EVT,
-	PIT_CONFIG_SAMSUNG_DVT,
-	PIT_CONFIG_ELPIDA_DVT,
-	PIT_CONFIG_SAMSUNG_PVT,
-	PIT_CONFIG_ELPIDA_PVT,
-	PIT_CONFIG_SAMSUNG_MP,
-	PIT_CONFIG_ELPIDA_MP,
-	PIT_CONFIG_RSVD,
-};
-
-struct {
-	enum mvl3 id0, id1;
-	enum board_config config;
-} id_map[] = {
-	/*  ID0      ID1         config */
-	{ LOGIC_0, LOGIC_0, PIT_CONFIG_SAMSUNG_MP },
-	{ LOGIC_0, LOGIC_1, PIT_CONFIG_ELPIDA_MP },
-	{ LOGIC_1, LOGIC_0, PIT_CONFIG_SAMSUNG_DVT },
-	{ LOGIC_1, LOGIC_1, PIT_CONFIG_ELPIDA_DVT },
-	{ LOGIC_0, LOGIC_Z, PIT_CONFIG_SAMSUNG_PVT },
-	{ LOGIC_1, LOGIC_Z, PIT_CONFIG_ELPIDA_PVT },
-	{ LOGIC_Z, LOGIC_0, PIT_CONFIG_SAMSUNG_MP },
-	{ LOGIC_Z, LOGIC_Z, PIT_CONFIG_ELPIDA_MP },
-	{ LOGIC_Z, LOGIC_1, PIT_CONFIG_RSVD },
-};
-
-static int board_get_config(void)
-{
-	int i;
-	int id0, id1;
-	enum board_config config = PIT_CONFIG_UNKNOWN;
-
-	id0 = gpio_read_mvl3(BOARD_ID0_GPIO);
-	id1 = gpio_read_mvl3(BOARD_ID1_GPIO);
-	if (id0 < 0 || id1 < 0)
-		return -1;
-
-	for (i = 0; i < ARRAY_SIZE(id_map); i++) {
-		if (id0 == id_map[i].id0 && id1 == id_map[i].id1) {
-			config = id_map[i].config;
-			break;
-		}
-	}
-
-	return config;
-}
-
-struct mem_timings *get_mem_timings(void)
-{
-	int i;
-	enum board_config config;
-	enum ddr_mode mem_type;
-	unsigned int frequency_mhz;
-	enum mem_manuf mem_manuf;
-	const struct mem_timings *mem;
-
-	config = board_get_config();
-	switch (config) {
-	case PIT_CONFIG_ELPIDA_EVT:
-	case PIT_CONFIG_ELPIDA_DVT:
-	case PIT_CONFIG_ELPIDA_PVT:
-	case PIT_CONFIG_ELPIDA_MP:
-		mem_manuf = MEM_MANUF_ELPIDA;
-		mem_type = DDR_MODE_DDR3;
-		frequency_mhz = 800;
-		break;
-	case PIT_CONFIG_SAMSUNG_EVT:
-	case PIT_CONFIG_SAMSUNG_DVT:
-	case PIT_CONFIG_SAMSUNG_PVT:
-	case PIT_CONFIG_SAMSUNG_MP:
-		mem_manuf = MEM_MANUF_SAMSUNG;
-		mem_type = DDR_MODE_DDR3;
-		frequency_mhz = 800;
-		break;
-	default:
-		printk(BIOS_CRIT, "Unknown board configuration.\n");
-		return NULL;
-	}
-
-	for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
-			i++, mem++) {
-		if (mem->mem_type == mem_type &&
-			mem->frequency_mhz == frequency_mhz &&
-			mem->mem_manuf == mem_manuf)
-			return (struct mem_timings *)mem;
-	}
-
-	return NULL;
-}
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 8a5a1dd908..1ff8d51de2 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -130,7 +130,7 @@ static void setup_gpio(void)
 
 static void setup_memory(struct mem_timings *mem, int is_resume)
 {
-	printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n",
+	printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n",
 	       mem->mem_manuf,
 	       mem->mem_type,
 	       mem->mpll_mdiv,
@@ -148,27 +148,97 @@ static void setup_memory(struct mem_timings *mem, int is_resume)
 	}
 }
 
-static struct mem_timings *setup_clock(void)
+#define PRIMITIVE_MEM_TEST 0
+#if PRIMITIVE_MEM_TEST
+static unsigned long primitive_mem_test(void)
 {
-	struct mem_timings *mem = get_mem_timings();
-	if (!mem) {
-		die("Unable to auto-detect memory timings\n");
+	unsigned long *l = (void *)0x40000000;
+	int bad = 0;
+	unsigned long i;
+	for(i = 0; i < 256*1048576; i++){
+		if (! (i%1048576))
+			printk(BIOS_SPEW, "%lu ...", i);
+		l[i] = 0xffffffff - i;
 	}
 
-	system_clock_init();
+	for(i = 0; i < 256*1048576; i++){
+		if (! (i%1048576))
+			printk(BIOS_SPEW, "%lu ...", i);
+		if (l[i] != (0xffffffff - i)){
+			printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i);
+			bad++;
+		}
+	}
+
+	printk(BIOS_SPEW, "%d errors\n", bad);
 
-	return mem;
+	return bad;
 }
+#else
+#define primitive_mem_test()
+#endif
+
+#define SIMPLE_SPI_TEST 0
+#if SIMPLE_SPI_TEST
+/* here is a simple SPI debug test, known to fid trouble */
+static void simple_spi_test(void)
+{
+	struct cbfs_media default_media, *media;
+	int i, amt = 4 * MiB, errors = 0;
+	//u32 *data = (void *)0x40000000;
+	u32 data[1024];
+	u32 in;
+
+	amt = sizeof(data);
+	media = &default_media;
+	if (init_default_cbfs_media(media) != 0) {
+		printk(BIOS_SPEW, "Failed to initialize default media.\n");
+		return;
+	}
+
+
+	media->open(media);
+	if (media->read(media, data, (size_t) 0, amt) < amt){
+		printk(BIOS_SPEW, "simple_spi_test fails\n");
+		return;
+	}
+
+
+	for(i = 0; i < amt; i += 4){
+		if (media->read(media, &in, (size_t) i, 4) < 1){
+			printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i);
+			return;
+		}
+		if (data[i/4] != in){
+		  errors++;
+			printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n",
+			       i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in);
+			/* reread it to see which is wrong. */
+			if (media->read(media, &in, (size_t) i, 4) < 1){
+				printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i);
+				return;
+			}
+			printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n",
+			       i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in);
+		}
+
+	}
+	printk(BIOS_SPEW, "%d errors\n", errors);
+}
+#else
+#define simple_spi_test()
+#endif
 
 void main(void)
 {
-	struct mem_timings *mem;
+
+	extern struct mem_timings mem_timings;
 	void *entry;
 	int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
 
 	/* Clock must be initialized before console_init, otherwise you may need
 	 * to re-initialize serial console drivers again. */
-	mem = setup_clock();
+	system_clock_init();
 
 	console_init();
 
@@ -176,7 +246,9 @@ void main(void)
 		setup_power();
 	}
 
-	setup_memory(mem, is_resume);
+	setup_memory(&mem_timings, is_resume);
+
+	primitive_mem_test();
 
 	if (is_resume) {
 		wakeup();
@@ -186,9 +258,12 @@ void main(void)
 	setup_gpio();
 	setup_graphics();
 
+	simple_spi_test();
 	/* Set SPI (primary CBFS media) clock to 50MHz. */
+	/* if this is uncommented SPI will not work correctly. */
 	clock_set_rate(PERIPH_ID_SPI1, 50000000);
-
+	simple_spi_test();
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	simple_spi_test();
 	stage_exit(entry);
 }