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author | Matt DeVillier <matt.devillier@gmail.com> | 2017-11-01 00:29:34 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-11-03 21:57:52 +0000 |
commit | e3d8471a7817250ee3f9e68d5612fa26d380825b (patch) | |
tree | 052175352a9c24bccbdc3cff4a74fec1d18b9407 /src/mainboard | |
parent | 158170b0a8128780df7dded2e24be067133c8a7d (diff) |
google/reks: override USB2 Phy settings on BSW D-Stepping SOC
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...
Base on Intel recommendation, override following
settings for USB2 port 1/2/3 on BSW D-stepping SOC.
1. Set USB[1] register for right side to 7321
2. Set USB[2] register for left side to 7021
3. Set USB[3] register for CCD to 7021
Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/google/cyan/variants/reks/Makefile.inc | 1 | ||||
-rw-r--r-- | src/mainboard/google/cyan/variants/reks/ramstage.c | 40 |
2 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index db2eea3d29..da5b5cc153 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c +ramstage-y += ramstage.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/cyan/variants/reks/ramstage.c b/src/mainboard/google/cyan/variants/reks/ramstage.c new file mode 100644 index 0000000000..27f9dfa241 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/ramstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> + +void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ + if (SocStepping() >= SocD0) { + //D-Stepping + //USB2[1] right external port + params->Usb2Port1PerPortPeTxiSet = 7; + params->Usb2Port1PerPortTxiSet = 3; + params->Usb2Port1IUsbTxEmphasisEn = 2; + params->Usb2Port1PerPortTxPeHalf = 1; + + //USB2[2] left external port + params->Usb2Port2PerPortPeTxiSet = 7; + params->Usb2Port2PerPortTxiSet = 0; + params->Usb2Port2IUsbTxEmphasisEn = 2; + params->Usb2Port2PerPortTxPeHalf = 1; + + //USB2[3] CCD + params->Usb2Port3PerPortPeTxiSet = 7; + params->Usb2Port3PerPortTxiSet = 0; + params->Usb2Port3IUsbTxEmphasisEn = 2; + params->Usb2Port3PerPortTxPeHalf = 1; + } +} |