cpu/intel/haswell: Move chip_ops to cpu cluster

The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.

Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

16 files changed, 43 insertions, 107 deletions

diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index 7667392c1e..e9a987651c 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -3,12 +3,8 @@ chip northbridge/intel/haswell
 	# This mainboard has VGA
 	register "gpu_ddi_e_connected" = "1"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb
index 144c2475ad..d84c471bae 100644
--- a/src/mainboard/asrock/h81m-hds/devicetree.cb
+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb
@@ -3,12 +3,8 @@
 chip northbridge/intel/haswell
 	register "gpu_ddi_e_connected" = "1"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 440efdfd69..2ded45256d 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -14,14 +14,10 @@ chip soc/intel/broadwell
 
 	register "ec_present" = "true"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			register "s0ix_enable" = "1"
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+		register "s0ix_enable" = "1"
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index 75bf8ee20f..be96e95d1f 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -11,13 +11,10 @@ chip soc/intel/broadwell
 
 	register "dq_pins_interleaved" = "true"
 
-	device cpu_cluster 0 on
-		chip cpu/intel/haswell
-			register "s0ix_enable" = "0"
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on end
 
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+		register "s0ix_enable" = "0"
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index cfb48123b4..3de469ecac 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -12,19 +12,17 @@ chip soc/intel/broadwell
 		.backlight_pwm_hz	= 200,
 	}"
 
-	device cpu_cluster 0 on
-		chip cpu/intel/haswell
-			# Disable S0ix for now
-			register "s0ix_enable" = "0"
-
-			register "vr_config" = "{
-				.slow_ramp_rate_set    = 3,
-				.slow_ramp_rate_enable = true,
-			}"
-
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on end
+
+		# Disable S0ix for now
+		register "s0ix_enable" = "0"
+
+		register "vr_config" = "{
+			.slow_ramp_rate_set    = 3,
+			.slow_ramp_rate_enable = true,
+		}"
+
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 9704cc34d3..18ec581fc0 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -13,13 +13,8 @@ chip northbridge/intel/haswell
 
 	register "usb_xhci_on_resume" = "true"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index fe09566dbb..59cf071629 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -11,12 +11,8 @@ chip soc/intel/broadwell
 
 	register "dq_pins_interleaved" = "true"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index d09d7a16ea..0c1222c4e8 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -15,13 +15,8 @@ chip northbridge/intel/haswell
 
 	register "usb_xhci_on_resume" = "true"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb
index ee3209a945..6a8e919ef3 100644
--- a/src/mainboard/hp/folio_9480m/devicetree.cb
+++ b/src/mainboard/hp/folio_9480m/devicetree.cb
@@ -13,12 +13,8 @@ chip northbridge/intel/haswell
 		.backlight_pwm_hz	= 200,
 	}"
 	register "usb_xhci_on_resume" = "true"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
index d5b566d941..3226170008 100644
--- a/src/mainboard/intel/baskingridge/devicetree.cb
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -11,13 +11,8 @@ chip northbridge/intel/haswell
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 0becbbf840..3b3a9750aa 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -9,12 +9,8 @@ chip soc/intel/broadwell
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops
diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
index 85c484be55..fc00734b5e 100644
--- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
@@ -13,12 +13,8 @@ chip northbridge/intel/haswell
 		.backlight_pwm_hz	= 220,
 	}"
 	register "ec_present" = "true"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
index ef4668c7a4..292a30df60 100644
--- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
+++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
@@ -13,12 +13,8 @@ chip northbridge/intel/haswell
 		.backlight_pwm_hz	= 220,
 	}"
 	register "ec_present" = "true"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb
index 429269cb96..f72ed9ff1b 100644
--- a/src/mainboard/msi/h81m-p33/devicetree.cb
+++ b/src/mainboard/msi/h81m-p33/devicetree.cb
@@ -2,12 +2,8 @@
 
 chip northbridge/intel/haswell
 	register "gpu_ddi_e_connected" = "1"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index ae98c9e79b..45350b6c13 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -20,12 +20,8 @@ chip soc/intel/broadwell
 		.backlight_pwm_hz	= 200,
 	}"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops
diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb
index 959c3b81db..8625daabfa 100644
--- a/src/mainboard/supermicro/x10slm-f/devicetree.cb
+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb
@@ -2,12 +2,8 @@
 
 chip northbridge/intel/haswell
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on