mb/asus/p8h61-m_pro_cm6630: Add initial support

This motherboard is somewhat similar to the p8h61-m_pro, but also different.
It has two exposed RAM slots with a pinout for four, and it's an OEM
variant used in PCs ASUS sold in stores.

Signed-off-by: Hunter Sell <alicelyralain@gmail.com>
Change-Id: Id08349feb0aeaf21406f814f6d19bbe0d9312a4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

11 files changed, 461 insertions, 0 deletions

diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index 529dd11d95..aed784a2ba 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -24,6 +24,7 @@ config VARIANT_DIR
 	default "p8h61-m_lx"       if BOARD_ASUS_P8H61_M_LX
 	default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0
 	default "p8h61-m_pro"      if BOARD_ASUS_P8H61_M_PRO
+	default "p8h61-m_pro_cm6630" if BOARD_ASUS_P8H61_M_PRO_CM6630
 
 config MAINBOARD_PART_NUMBER
 	string
@@ -31,6 +32,7 @@ config MAINBOARD_PART_NUMBER
 	default "P8H61-M LX"       if BOARD_ASUS_P8H61_M_LX
 	default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
 	default "P8H61-M PRO"      if BOARD_ASUS_P8H61_M_PRO
+	default "P8H61-M PRO CM6630" if BOARD_ASUS_P8H61_M_PRO_CM6630
 
 config OVERRIDE_DEVICETREE
 	string
diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name
index 087dd9236e..0956f40c2e 100644
--- a/src/mainboard/asus/h61-series/Kconfig.name
+++ b/src/mainboard/asus/h61-series/Kconfig.name
@@ -38,3 +38,15 @@ config BOARD_ASUS_P8H61_M_PRO
 	select REALTEK_8168_RESET
 	select RT8168_SET_LED_MODE
 	select SUPERIO_NUVOTON_NCT6776
+
+config BOARD_ASUS_P8H61_M_PRO_CM6630
+	bool "P8H61-M PRO CM6630"
+	select BOARD_ASUS_H61_SERIES
+	select BOARD_ROMSIZE_KB_4096
+	select DRIVERS_ASMEDIA_ASPM_BLACKLIST
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select MAINBOARD_HAS_LPC_TPM
+	select REALTEK_8168_RESET
+	select RT8168_SET_LED_MODE
+	select SUPERIO_NUVOTON_NCT6776
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/board_info.txt b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/board_info.txt
new file mode 100644
index 0000000000..aa785ec58e
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.asus.com/Desktop/Entertainment/CM6630
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/cmos.default b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/cmos.default
new file mode 100644
index 0000000000..6f3cec735e
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=32M
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/cmos.layout b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/cmos.layout
new file mode 100644
index 0000000000..8aa0acfe95
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/cmos.layout
@@ -0,0 +1,65 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+409	2	e	7	power_on_after_fail
+
+421	2	e	9	sata_mode
+
+# coreboot config options: northbridge
+432	3	e	11	gfx_uma_size
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+9	0	AHCI
+9       1       Compatible
+9	2	Legacy
+11	0	32M
+11	1	64M
+11	2	96M
+11	3	128M
+11	4	160M
+11	5	192M
+11	6	224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 439 984
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/data.vbt b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/data.vbt
new file mode 100644
index 0000000000..114a840660
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/data.vbt
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c
new file mode 100644
index 0000000000..af90702cfe
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin states. */
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x30);
+	pnp_write_config(GLOBAL_DEV, 0x27, 0x40);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x20);
+
+	/* Power RAM in S3. */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	pnp_set_logical_device(SERIAL_DEV);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Enable UART */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x51, id_only);
+	read_spd(&spd[2], 0x53, id_only);
+}
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/gma-mainboard.ads
new file mode 100644
index 0000000000..98af657fb9
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI3, -- mainboard HDMI port
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/gpio.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/gpio.c
new file mode 100644
index 0000000000..725e4fa282
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/gpio.c
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_OUTPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_NATIVE,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
new file mode 100644
index 0000000000..129797b6c1
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
+	0x10438444,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10438444),
+	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01456130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel HDMI */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb
new file mode 100644
index 0000000000..7882bf0748
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/overridetree.cb
@@ -0,0 +1,81 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		chip southbridge/intel/bd82x6x
+			register "gen1_dec" = "0x000c0291"	# HWM
+
+			device pci 1c.0 on  end	# PCIe x1 Port (PCIEX1_1)
+			device pci 1c.1 on  end	# PCIe x1 Port (PCIEX1_2)
+			device pci 1c.2 on	# Realtek RTL8111E Ethernet Controller
+				chip drivers/net
+					register "customized_leds" = "0x00f6"
+					register "wake" = "9"
+					device pci 00.0 on end
+				end
+			end
+			device pci 1c.3 on  end	# ASMedia ASM1042 USB3 Controller
+			device pci 1c.4 on  end # RP #6: ASM1083 PCI Bridge
+                        device pci 1c.5 on  end	# ASMedia ASM1062 SATA Controller
+			device pci 1c.6 off end	# Unused PCIe Port
+			device pci 1c.7 off end	# Unused PCIe Port
+
+			device pci 1f.0 on	# LPC bridge
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 on		# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 5
+						drq 0x74 = 4
+						irq 0xf0 = 0x3c
+					end
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2, IR
+					device pnp 2e.5 on		# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end		# CIR
+					device pnp 2e.7 off end		# GPIO6-9
+					device pnp 2e.8 off end		# WDT1, GPIO0, GPIO1, GPIOA
+					device pnp 2e.9 off end		# GPIO2-5
+					device pnp 2e.a on		# ACPI
+						irq 0xe5 = 0x06
+						irq 0xe6 = 0x0c
+						irq 0xe7 = 0x11
+						irq 0xf0 = 0x00
+						irq 0xf2 = 0x5d
+					end
+					device pnp 2e.b on		# HWM, LED
+						io 0x60 = 0x0290
+						io 0x62 = 0x0000
+					end
+					device pnp 2e.d on  end		# VID
+					device pnp 2e.e off end		# CIR WAKE-UP
+					device pnp 2e.f on		# GPIO Push-Pull or Open-drain
+						irq 0xf0 = 0x9d
+					end
+					device pnp 2e.14 off end	# SVID
+					device pnp 2e.16 on		# Deep Sleep
+						io 0x30 = 0x20
+					end
+					device pnp 2e.17 on		# GPIOA
+						irq 0xe0 = 0xff
+						irq 0xe1 = 0xff
+						irq 0xe2 = 0xff
+						irq 0xe3 = 0xff
+						irq 0xe5 = 0xff
+					end
+				end
+				chip drivers/pc80/tpm
+					device pnp 4e.0 on end	# TPM
+				end
+			end
+		end
+	end
+end