diff options
| author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-05-23 18:52:24 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-12 15:00:25 +0000 |
| commit | ce3c77c30536649ba2a6ab81979a7fa371128c31 (patch) | |
| tree | b3454b306a0f82b4c5030aae568808f7ae1786d1 /src/mainboard | |
| parent | 211e391a8295d48495ba5e4ebcde11ec85ed317f (diff) | |
mb/ibm/sbp1: Set coreboot ready GPIO in BS_PAYLOAD_BOOT
Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS
completion.
Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/ibm/sbp1/ramstage.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/ibm/sbp1/ramstage.c b/src/mainboard/ibm/sbp1/ramstage.c index 11d0a8b6d3..63481aa123 100644 --- a/src/mainboard/ibm/sbp1/ramstage.c +++ b/src/mainboard/ibm/sbp1/ramstage.c @@ -3,9 +3,19 @@ #include <soc/ramstage.h> #include "include/spr_sbp1_gpio.h" +#include <bootstate.h> void mainboard_silicon_init_params(FSPS_UPD *params) { /* configure Emmitsburg PCH GPIO controller after FSP-M */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } + +static void finalize_boot(void *unused) +{ + printk(BIOS_DEBUG, "FM_BIOS_POST_CMPLT_N cleared.\n"); + /* Clear FM_BIOS_POST_CMPLT_N */ + gpio_output(GPPC_C17, 0); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |