diff options
| author | Jon Murphy <jpmurphy@google.com> | 2022-06-28 10:36:23 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-04 14:02:26 +0000 |
| commit | c4e90454f4e3787c9e5d0b7aa758ee9b5757df4b (patch) | |
| tree | ad1a49b4477d62eb6604e3332b6ffc4a64daed06 /src/mainboard | |
| parent | dc86804a7db0ac67b81803d1662608320c8838a7 (diff) | |
treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/mainboard')
41 files changed, 41 insertions, 41 deletions
diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd index 7194632e36..bb2a95cd0f 100644 --- a/src/mainboard/google/asurada/chromeos.fmd +++ b/src/mainboard/google/asurada/chromeos.fmd @@ -1,4 +1,4 @@ -# Firmware Layout Description for Chrome OS. +# Firmware Layout Description for ChromeOS. # # The size and address of every section must be aligned to at least 4K, except: # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b985be20a9..228aecdff7 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -97,7 +97,7 @@ config CHROMEOS select HAS_RECOVERY_MRC_CACHE config CHROMEOS_WIFI_SAR - bool "Enable SAR options for Chrome OS build" + bool "Enable SAR options for ChromeOS build" depends on CHROMEOS select DSAR_ENABLE select GEO_SAR_ENABLE diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index de3337f399..ab4d210551 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 48a1fdd42d..e5c2e960b9 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -79,7 +79,7 @@ chip soc/intel/alderlake chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" - # Use Chrome OS privacy screen _HID + # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index cac72995bc..63fb2a901d 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -71,7 +71,7 @@ chip soc/intel/alderlake chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" - # Use Chrome OS privacy screen _HID + # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index a94410354b..6ac469af1f 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -570,7 +570,7 @@ chip soc/intel/alderlake end chip drivers/i2c/generic register "hid" = ""GOOG0020"" - register "desc" = ""Chrome OS HPS"" + register "desc" = ""ChromeOS HPS"" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL # HPS uses I2C addresses 0x30 and 0x51. diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index 9d9233b9d5..eed577710b 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -571,7 +571,7 @@ chip soc/intel/alderlake end chip drivers/i2c/generic register "hid" = ""GOOG0020"" - register "desc" = ""Chrome OS HPS"" + register "desc" = ""ChromeOS HPS"" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL # HPS uses I2C addresses 0x30 and 0x51. diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 4d7d6a5d13..3b92b63b49 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -99,7 +99,7 @@ chip soc/intel/alderlake chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" - # Use Chrome OS privacy screen _HID + # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 9a0eb1f6e8..60eb8a3d0d 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -85,7 +85,7 @@ chip soc/intel/alderlake chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" - # Use Chrome OS privacy screen _HID + # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb index 6f0eb2168e..3280b4be4f 100644 --- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb @@ -570,7 +570,7 @@ chip soc/intel/alderlake end chip drivers/i2c/generic register "hid" = ""GOOG0020"" - register "desc" = ""Chrome OS HPS"" + register "desc" = ""ChromeOS HPS"" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL # HPS uses I2C addresses 0x30 and 0x51. diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 5a964c6672..9a4de9393c 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -416,7 +416,7 @@ chip soc/intel/alderlake device ref i2c2 on chip drivers/i2c/generic register "hid" = ""GOOG0020"" - register "desc" = ""Chrome OS HPS"" + register "desc" = ""ChromeOS HPS"" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL # HPS uses I2C addresses 0x30 and 0x51. diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index f1074de74d..3ec57e47c8 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -320,7 +320,7 @@ chip soc/intel/alderlake device ref i2c2 on chip drivers/i2c/generic register "hid" = ""GOOG0020"" - register "desc" = ""Chrome OS HPS"" + register "desc" = ""ChromeOS HPS"" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL # HPS uses I2C addresses 0x30 and 0x51. diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 903b67f209..d8ef5096cc 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -94,7 +94,7 @@ chip soc/intel/alderlake chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" - # Use Chrome OS privacy screen _HID + # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" diff --git a/src/mainboard/google/cherry/chromeos.fmd b/src/mainboard/google/cherry/chromeos.fmd index 7194632e36..bb2a95cd0f 100644 --- a/src/mainboard/google/cherry/chromeos.fmd +++ b/src/mainboard/google/cherry/chromeos.fmd @@ -1,4 +1,4 @@ -# Firmware Layout Description for Chrome OS. +# Firmware Layout Description for ChromeOS. # # The size and address of every section must be aligned to at least 4K, except: # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. diff --git a/src/mainboard/google/corsola/chromeos.fmd b/src/mainboard/google/corsola/chromeos.fmd index a8c4dfe0af..5b2234d39e 100644 --- a/src/mainboard/google/corsola/chromeos.fmd +++ b/src/mainboard/google/corsola/chromeos.fmd @@ -1,4 +1,4 @@ -# Firmware Layout Description for Chrome OS. +# Firmware Layout Description for ChromeOS. # # The size and address of every section must be aligned to at least 4K, except: # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 396347d818..84626efee0 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -65,7 +65,7 @@ config CHROMEOS select VBOOT_LID_SWITCH config CHROMEOS_WIFI_SAR - bool "Enable SAR options for Chrome OS build" + bool "Enable SAR options for ChromeOS build" depends on CHROMEOS select DSAR_ENABLE select SAR_ENABLE diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index f88e2df55d..7b6066ef61 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -37,7 +37,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 40afdf4851..916a235de0 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -39,7 +39,7 @@ config CHROMEOS select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC config CHROMEOS_WIFI_SAR - bool "Enable SAR options for Chrome OS build" + bool "Enable SAR options for ChromeOS build" depends on CHROMEOS select DSAR_ENABLE select GEO_SAR_ENABLE diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 5556c989bb..62bed72961 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -33,7 +33,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 357f3bfe6f..a42e9dee82 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 01e94f2f77..287e42649c 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -33,7 +33,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl index 9579ae36f9..6c208cf6c6 100644 --- a/src/mainboard/google/guybrush/dsdt.asl +++ b/src/mainboard/google/guybrush/dsdt.asl @@ -15,7 +15,7 @@ DefinitionBlock ( #include <acpi/dsdt_top.asl> #include <soc.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 8270b147bb..2fc416e775 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -182,7 +182,7 @@ chip soc/amd/cezanne chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" - # Use Chrome OS privacy screen _HID + # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 749b0df30a..712ed06e7c 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -166,7 +166,7 @@ config CHROMEOS select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU config CHROMEOS_WIFI_SAR - bool "Enable SAR options for Chrome OS build" + bool "Enable SAR options for ChromeOS build" depends on CHROMEOS select DSAR_ENABLE select GEO_SAR_ENABLE diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 022a607a1d..dad2267c33 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -35,7 +35,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index be4033b270..7aa4ae01fe 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -52,7 +52,7 @@ DefinitionBlock ( /* Thermal handler */ #include <variant/acpi/thermal.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 2635854866..61d45b0816 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -1,4 +1,4 @@ -# Firmware Layout Description for Chrome OS. +# Firmware Layout Description for ChromeOS. # # The size and address of every section must be aligned to at least 4K, except: # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index bebee41b15..7ae3cc810c 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index dbba8064e0..950ac2e592 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -41,7 +41,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index fde3975521..79277c6380 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index fd91f64859..00def91566 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> #if CONFIG(EC_GOOGLE_WILCO) - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/skyrim/dsdt.asl b/src/mainboard/google/skyrim/dsdt.asl index 3aec6baf3d..39399d8eb7 100644 --- a/src/mainboard/google/skyrim/dsdt.asl +++ b/src/mainboard/google/skyrim/dsdt.asl @@ -15,7 +15,7 @@ DefinitionBlock ( #include <acpi/dsdt_top.asl> #include <soc.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 8947cd8bcf..926a0ca4b1 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -140,7 +140,7 @@ config VBOOT_GSCVD default n config CHROMEOS_WIFI_SAR - bool "Enable SAR options for Chrome OS build" + bool "Enable SAR options for ChromeOS build" depends on CHROMEOS select DSAR_ENABLE select GEO_SAR_ENABLE diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 66747d17c2..d4e9339954 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock( #include "mainboard.asl" } - // Chrome OS Embedded Controller + // ChromeOS Embedded Controller Scope (\_SB.PCI0.LPCB) { // ACPI code for EC SuperIO functions diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index c2df9b7310..e67a8dcfef 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -44,7 +44,7 @@ DefinitionBlock ( /* Thermal handler */ #include <variant/acpi/thermal.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index 4b41b22d6f..6449e26ca3 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -28,7 +28,7 @@ DefinitionBlock( } #if CONFIG(EC_GOOGLE_CHROMEEC) - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index f4169da46d..bc5f999f05 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 2097b3e39c..236762d75f 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( } #if CONFIG(EC_GOOGLE_CHROMEEC) - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index cebd048256..dd93b43da1 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( } #if CONFIG(EC_GOOGLE_CHROMEEC) - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl index 57324b3656..3e8f6e2fa8 100644 --- a/src/mainboard/intel/shadowmountain/dsdt.asl +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( } } - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { // ACPI code for EC SuperIO functions diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index ca1e441d10..785e985b6f 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -33,7 +33,7 @@ DefinitionBlock( } #if CONFIG(EC_GOOGLE_CHROMEEC) - /* Chrome OS Embedded Controller */ + /* ChromeOS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ |