diff options
| author | Jeremy Soller <jeremy@system76.com> | 2023-03-10 13:28:53 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-03 12:53:30 +0000 |
| commit | bfb35f2488b9d392847df1e1d64c0f2fd1c7eccc (patch) | |
| tree | cad7c3e19640a60fd7c472d675137c6b750aea0c /src/mainboard | |
| parent | 976e09b0210e5e8c9c883dd9ca094d1de000976e (diff) | |
mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI
This allows the EC to detect C10 using eSPI instead of a dedicated pin.
Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/system76/tgl-u/variants/darp7/ramstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/system76/tgl-u/variants/galp5/ramstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c | 3 |
3 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c index a60587d5d4..2b64f9f130 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c @@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[5] = 1; // J_TYPEC2 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c index a60587d5d4..2b64f9f130 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c @@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[5] = 1; // J_TYPEC2 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c index 2064836977..8b80740294 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c @@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[2] = 1; // J_TYPEC1 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } |