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| author | Curtis Chen <curtis.chen@intel.com> | 2021-12-23 18:02:02 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-10 14:27:41 +0000 |
| commit | b7d1b35175db3bc895c511125626cb87442d33c6 (patch) | |
| tree | a4c40a69c923e479a5e411c67f75467a4102fb1d /src/mainboard | |
| parent | 150fee60cc6f30fe3dddcf504958cd2b916f469b (diff) | |
mb/google/brya/var/brask: Update PL and PsysPL
Update all the ADL-P 15W/28W/45W SKU's PL and PsysPL. These config
values are generated iPDG application with ADL-P platform package
tool. RDC Kit ID for the iPDG tools:
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Libraries: 613643
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.
BUG=b:211365920
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I4a827ae40e26294db20d5d1b2121dcce5118e290
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/ramstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c index f5105fea2c..c2a5ec3818 100644 --- a/src/mainboard/google/brya/variants/brask/ramstage.c +++ b/src/mainboard/google/brya/variants/brask/ramstage.c @@ -10,20 +10,26 @@ const struct cpu_power_limits limits[] = { /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, }; const struct system_power_limits sys_limits[] = { /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 135 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 230 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, }; |