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authorAaron Durbin <adurbin@chromium.org>2015-08-05 12:26:56 -0500
committerAaron Durbin <adurbin@chromium.org>2015-08-14 15:18:23 +0200
commitabf87a25f21b22797d8dc8c9a33537980df2c24d (patch)
tree40d1849a90a9151b9bc11deac619698f465ba172 /src/mainboard
parenta0429b6f3ca6aa63124dbbbe3507629adc9ccd23 (diff)
intel/common: use external stage cache for fsp_ramstage
The fsp_ramstage.c code was not taking advantage of the stage cache which does all the accounting and calculation work for the caller. Remove the open coded logic and use the provided infrastructure. Using said infrastructure means there's no need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove it. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290831 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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